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Unformatted text preview: ECE3801  Advanced Logic Circuits
Homework 5: Due Monday 4 May 2009 Be sure to attach cover sheet for proper grading and return!
Always complete the reading assignments before attempting the homework problems.
Show all of your work. Underline, circle or box each result. Always write neatly. The grader can not be expected to GUESS what your doing!
Points are as indicated. 1) Katz Problem 6.18. (10 pts) 2) The figure below shows a multiﬂip ﬂop synchronizer circuit which clocked using a
synchronous counter to divide down the system clock. The counter can be setup to divide by
1, 2, 3 or 4. Assume the propagation delay through the counter is always 9 ns. All the other
ﬂipﬂops have the following timing parameters 7 _<_ 03%) g 10 ns, thozd=1.0 ns and tsetup=3.5 ns. (20 pts) a. What is clock skew and how does it effect a synchronous circuit? b. What is the maximum amount of clock skew the “Synchronous System” can
handle if 5 5 tnand g 8 ns? 0. Will this divided clock synchronizer cause excessive clock skew for the
“Synchronous System”? Why or why not? synchronizer ASYNCIN
(asynchronous
input) Fc u:
(system clock) 3) Katz Problems 6.120 and 6.21 (20 pts) 4) For the circuit below, assume that tsetup = 8 ns and tpd = 10.0 ns. What is the purpose of
FF3? Sketch the output of FF3 (alone) for a 10 MHz system clock. (10 pts) D3: CLksyn‘ _ 5) For the same circuit, calculate the MTBF pf the synchronizer using the following values for
fclk and asynchronous input transition rates, a, and assuming the given ﬂip ﬂip logic family types. Explain the meaning of the resulting MTBF's as a function of fc1k and a and logic family.
(25 pts) a. fc1k=31 MHz and a=0.7 MHz, assuming ﬂip ﬂops are 74LS74 (1:21.35 ns and To=4.8E3)
b. fc1k=40 MHz and a=0.7 MHz, assuming ﬂip ﬂops are 74LS74 (t=1.35 ns and To=4.8E3) c. fc1k=31 MHz and a=0.7 MHz, assuming ﬂip ﬂops = 74ALS74 (17:1.0 ns and To=8.7E6)
d. fc1k=31 MHZ and a= 7.0 MHz, assuming ﬂip ﬂops = 74ALS74 (t=1.0 ns and To=8.7E6)
e. fc1k=40 MHZ and a=0.7 MHz, assuming ﬂip ﬂops = 74ALS74 (121.0 ms and To=8.7E6) 6) Programmable logic design environments like Xilinx sometimes implement simple
combinational circuits using small ROMS. We all know Xilinx can be annoying to work with
but it typically implements basic logic correctly. (15 pts) a. Explain how and why a memory device can also be a combinational circuit? b. A certain combinational logic system is to be implemented using a small ROM. The system
has 3 inputs A, B, and C and three outputs D0, D1, and D2. Standard EEPROM's have word sizes that are powers of 2. What size standard EEPROM will be required to implement this
system? c. Sketch your EEPROM showing all address lines, all output lines, an active low output enable (OE) and an active low chip select (CS). Appropriately label the inputs and outputs
A,B,C and D02. d. Show the full contents of your EEPROM in the table like the one below.
D0 = A' + BC D1: 3' D2 = EABcQ, 3, 6) ‘ Address ‘ Contents ECE3801 Homework #5 Submitted by: ECE BOX #: Date: Question Grade
1 (20)
2 (20)
3 (15)
4 (20)
5 (15)
6 (15) Total: ...
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 Spring '08
 Jarvis

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