4902_C2007__pll_lab

4902_C2007__pll_lab - PLL This is the most complicated of...

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PLL This is the most complicated of the three optional labs - but is definitely the coolest system and if you can get it working, you should be able to learn a lot. The top level block diagram of the PLL is shown below: The system blocks and their input and output signals are as follows: SYSTEM INPUT REFCLK Reference clock 0 to +5V clock signal OUTPUT VCOCLK VCO clock 0 to +5V clock signal For the basic VCO, the purpose is to produce an output clock signal VCOCLK that is the same frequency and phase as the input. PHASE-FREQUENCY DETECTOR (PFD) REFCLK Reference clock 0 to +5V clock signal INPUT VCOCLK VCO clock 0 to +5V clock signal UP VCO freq UP 0 to +5V signal, active high OUTPUT /DOWN VCO freq DOWN 0 to +5V signal, active low The phase-frequency detector compares the incoming rising edges of the reference clock and VCO clock. If the reference clock edge arrives first, an UP pulse is sent to the loop filter indicating that the VCO needs to speed up to bring the VCO clock into lock with the reference clock. If the VCO clock edge arrives first, then the VCO is running too fast and a /DOWN pulse is sent to the loop filter indicating that the VCO needs to slow down to bring the VCO clock into lock with the reference clock. When the two clocks are locked in phase and frequency then the UP and /DOWN signals are very narrow pulses of equal duration that essentially cancel each other out, leaving the VCO frequency unchanged.
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4902_C2007__pll_lab - PLL This is the most complicated of...

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