4902C2001exam3 - Name _______________________ ECE Box #...

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Unformatted text preview: Name _______________________ ECE Box # _____________ Problem Score Points 1 2 3 4 ______ ______ ______ ______ 36 30 16 18 EE4902 C2001 Analog IC Design Exam 3 • This is a closed book test! • Show all your work. Partial credit may be given. If you think you need something that you can't remember, write down what you need and what you'd do if you remembered it. • Look for the simple, straightforward way to solve the problem for the level of accuracy required. Don't get entangled in unnecessary algebra. • You may assume all op-amps to be ideal, except as otherwise noted. • As in real life, some problems may give you more information than you need. Don't assume that all information must be used! It's your job to decide what's relevant to the solution. • You will have 55 minutes to complete this exam. are four problems on a total of 11 pages. There 1 2 MOSFET LARGE SIGNAL CHARACTERISTICS N CHANNEL P CHANNEL - S VGS G+ + VGD - D CIRCUIT SYMBOL - D VGD G+ + VGS - S ID + VDS - VDS + ID ACTIVE I D = µnCox W (VGS - Vtn) 2 [1 + ln (VDS - Veff )] I D = µpCox W (VGS - Vtp )2 [1 + lp |VDS - Veff| ] 2 L Veff 2 L Veff VDS > Veff ACTIVE ID VDS < Veff VDS < Veff ACTIVE VDS > Veff TRIODE ID ID-VDS CHARACTERISTIC TRIODE INCREASING VGS DECREASING VGS VDS VGS < Vtn OFF VDS VGS > Vtp OFF ID ID Vtn Vtp ID-VGS CHARACTERISTIC (ACTIVE REGION) VGS VGS < Vtn OFF VGS VGS < Vtp ACTIVE VGS > Vtn ACTIVE VGS > Vtp OFF TRIODE REGION I D = µnCox W [ (VGS - Vtn)VDS - VDS ] L 2 2 I D = µpCox W [ (VGS - Vtp)VDS - VDS ] L 2 2 3 1. This problem is concerned with the op-amp circuit shown in Figure 1. The op-amp is connected as a unity gain follower with a 1V DC input. For the purposes of this problem, you may ignore channel length modulation effects and the body effect. Use the following MOSFET parameters for the AMI 1.2µm process: Parameter N-channel +0.61 7.42E-5 P-channel -0.83 1.93E-5 V A/V2 Units Vt µCox VDD = +5V M3 72 2.4 VG3 M4 72 2.4 VG5 M5 360 2.4 VIN + +1V M1 6.4 2.4 M2 6.4 2.4 CCOMP 60pF VOUT VS1 20µA M6 8.5 2.4 VG6 M7 34 2.4 M8 85 2.4 VSS = -5V Figure 1a. VIN + +1V VOUT Figure 1b. 4 a) Find the DC drain current ID (accuracy ±10%) for all MOSFETs. Use the table below to record your answers. [12] DC Current ID [µA] M1 M2 M3 M4 M5 M6 M7 M8 b) Find the DC node voltages (accuracy ±50mV) for all nodes. Use the table below to record your answers. [12] Node voltage [V] VIN VOUT VS1 VG3 VG5 VG6 c) Will this op-amp exhibit a systematic offset? YES NO [1] [5] EXPLAIN! d) What is the slew rate (accuracy ±10%) for this op-amp? Slew Rate = __________ [6] 5 2. The small-signal model of a two stage op-amp is shown below: Vout + Vid gmI Vid gmI = 3E-5 A/V a) RoI 6.7MΩ CI 2pF + V1 gmII V1 gmI I = 6E-4 A/V [6] RoII 85kΩ CII 20pF Determine the open-loop DC gain A0 (accuracy ±10%): A0 = __________ b) On the following page, plot the magnitude and phase Bode plots for the open loop gain transfer function A(f)= vout/vin. [12] c) With feedback for a closed-loop gain of unity, will this op-amp be stable or unstable? [1] STABLE UNSTABLE EXPLAIN! [5] NOTE: WHICH PART (d) YOU ANSWER DEPENDS ON YOUR ANSWER TO (c)!!! ONLY ANSWER ONE OF THE QUESTIONS BELOW!!! d) [6] IF YOU SAID STABLE fl IF YOU SAID UNSTABLE fl Determine the gain-bandwidth product fT: fT = _______ Describe qualitatively what design change(s) would be necessary to stabilize the op-amp: 6 7 3. One problem with the simple two-stage op-amp you built in Lab 3 is the high output impedance. That's why you had to use feedback resistors of 1MΩ and 100kΩ in the gain of +11 amplifier -- lower values would have loaded down the output stage, reducing open-loop gain and drawing too much current. One solution to this problem is to add a source follower buffer at the output stage, as shown in the op-amp circuit below (compensation capacitor omitted for simplicity). M9 is the source follower transistor; M10 is a current source to provide DC bias current for M9. VDD = +5V M3 M4 M5 M9 VIN1 M1 M2 VIN2 VOUT VDD = +5V M6 M7 M8 M10 VSS = -5V 8 a) Identify the inverting and non-inverting inputs. Inverting: __________ Non-inverting: __________ [8] b) The maximum and minimum limits on the input common mode voltage (defined as VICM = (vIN1 + vIN2)/2) and the output voltage vOUT are determined by the condition that all MOSFETs operate in the active region. As you may recall from lecture, lab, and problem sets, at each limit one transistor "crashes" into the triode region. This part of the problerm requires no numerical calculation! For each voltage limit case below, just tell which transistor crashing into triode determines the voltage limit. [8] Voltage Limit Condition MOSFET "crashing" Common mode voltage, maximum (VICM+) Common mode voltage, minimum (VICM-) Output voltage, maximum Output voltage, minimum M____ M____ M____ M____ 9 4. This problem considers two implementations of a cascode current source, shown in Figs. 4a and 4b. For the purposes of this problem, you may ignore channel length modulation effects and the body effect. Also, assume that all P-channel devices are operating in the active region; this problem is concerned with the N-channel devices making up the cascoded current mirror. Use the following MOSFET parameters for a typical MC14007: Parameter N-channel +1.70 3.5E-5 V A/V2 Units Vt µCox The "traditional" cascode current source (shown in Fig. 4a) is great for achieving very high small-signal output impedance. Unfortunately, the tradeoff in reduced signal range (due to the compliance voltage limit) is severe. This can be especially troublesome in low-supply-voltage environments, such as with the single +5V supply rail shown in Fig. 4a. VDD = +5V 100µA 100µA VOUT 100µA M4 160 10 M2 160 10 M3 160 10 M1 160 10 Fig. 4a a) For the circuit in Fig. 4a, determine the minimum limit VMIN(a) of the voltage compliance range (that is, the minimum voltage at VOUT for which all MOSFETs are in the active region). Accuracy ±50mV. VMIN(a) = __________ [6] 10 The problem with the cascode current source shown in Fig. 4a is that the gate of the cascode transistor M4 is set to a higher voltage than it needs to be. M1 and M2 realy do need to be connected in a mirror configuration. But the only purpose of M3 is to set the DC voltage at the gate of M4. We can get better output voltage compliance if we use the approach shown in Fig. 4b. VDD = +5V 100µA 100µA 100µA VOUT 100µA M4 160 10 M5 W5 10 M1 160 10 Fig. 4b b) M2 160 10 For the circuit in Fig. 4b, determine the minimum possible limit VMIN(b) of the voltage compliance range (that is, the minimum voltage at VOUT for which all MOSFETs are in the active region) AND the required with W5 of M5 to achieve this limit. VMIN(b) = __________ W5 = __________ [12] 11 ...
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This note was uploaded on 10/13/2009 for the course ECE 4902 taught by Professor Mcneill during the Spring '01 term at WPI.

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