4902C2002exam1

4902C2002exam1 - Name _______________________ ECE Box #...

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Unformatted text preview: Name _______________________ ECE Box # _____________ Problem Score Points 1 2 3 4 ______ ______ ______ ______ 30 30 20 20 EE4902 C2002 Analog IC Design Exam 1 • This is a closed book test! • Show all your work. Partial credit may be given. If you think you need something that you can't remember, write down what you need and what you'd do if you remembered it. • Look for the simple, straightforward way to solve the problem for the level of accuracy required. Don't get entangled in unnecessary algebra. • You may assume all op-amps to be ideal, except as otherwise noted. • As in real life, some problems may give you more information than you need. Don't assume that all information must be used! It's your job to decide what's relevant to the solution. • You have until 12 noon to complete this exam. four problems on a total of 13 pages. There are 1 2 MOSFET LARGE SIGNAL CHARACTERISTICS N CHANNEL P CHANNEL CIRCUIT SYMBOL D G ID B - D VGD G+ + VGS - S ID + VDS G S B + S VSG G+ VGD - D + VSD - S D ID ID ACTIVE I D = µnCox W (VGS - Vtn) 2 [1 + ln (VDS - Veff )] I D = µpCox W (VSG + Vtp )2 [1 + lp (VSD - Veff)] 2 L Veff 2 L Veff VDS > Veff ACTIVE ID VDS < Veff ID VSD < Veff TRIODE VSD > Veff ACTIVE ID-VDS CHARACTERISTIC TRIODE INCREASING VGS INCREASING VSG VDS VGS < Vtn OFF VDS VSG < -Vtp OFF ID ID Vtn Vtn ID-VGS CHARACTERISTIC (ACTIVE REGION) VGS VGS < Vtn OFF VGS VSG < -Vtp OFF VGS > Vtn ACTIVE VSG > -Vtp ACTIVE TRIODE REGION I D = µnCox W [ (VGS - Vtn)VDS - VDS ] L 2 2 I D= µpCox W [ (VSG + Vtp)VSD - VSD ] L 2 2 3 1. For each circuit configuration, indicate i) the operating region of the MOSFET: cutoff, triode, active ii) indicate the dopant type (n or p) in the source, body, and drain regions by writing "n" or "p" in the box in each region on the cross-sectional view of the MOSFET iii) sketch the distribution of mobile charge (if any) in the channel under the gate, and indicate if the charge is holes or electrons [10] a) Operating Region: CUTOFF TRIODE ACTIVE 4 [10] b) Operating Region: CUTOFF TRIODE ACTIVE [10] c) Operating Region: CUTOFF TRIODE ACTIVE 5 2. This problem involves design of a circuit both electrically (choosing the input bias voltage) and physically (choosing the MOSFET width) to achieve a desired large signal operating point at the output as well as a specified small signal gain. The circuit is shown in Figure 2a. You may assume that the substrate (body) terminal is tied to the source terminal. You may also assume channel length modulation to be negligible (l=0). Use the following MOSFET parameters for this 2µm process: Parameter N-channel +1.10 5.2E-5 P-channel -1.20 1.5E-5 V A/V2 Units Vt µCox a) Determine MOSFET width W and input bias voltage VBIAS to achieve an output DC bias level of VOUT = +2.5V and a small signal gain magnitude |vout/vin|=10. [12] W = _______ VBIAS = _______ vDD = +5V RD 20kΩ vout + W 2µm vin - VBIAS Figure 2a. 6 b) Using the axes below, sketch the total output vOUT when vin is a 0.1V peak sine wave. Be sure to indicate numerical values for any interesting voltage levels (for example, approximate maximum and minimum values of vOUT). [6] VOUT t VIN 0.1 V pk VBIAS t c) Using the axes below, sketch the total output vOUT when vin is a 1V peak sine wave. Be sure to indicate numerical values for any interesting voltage levels (for example, approximate maximum and minimum values of vOUT). [6] VOUT t VIN 1 V pk VBIAS t MORE ON THE NEXT PAGE!!! 7 8 d) Your design from part (a) is modified by inserting resistor RS in series with the source, as shown in Figure 2b. With the same MOSFET width W, VBIAS is adjusted to a new value VBIAS' so that the DC operating point at the output remains the same and the MOSFET is still in the active region. Will the small-signal gain decrease, remain the same, or increase? [1] DECREASE REMAIN THE SAME INCREASE EXPLAIN! [5] vDD = +5V RD 20kΩ vout + W 2µm RS 10kΩ vin - VBIAS' Figure 2b. 9 3. In most of the op-amp circuits you've worked with so far, you have probably used dual power supplies - for example, the +15V and -15V supply rails in most of the labs in EE3204 (Microelectronics II). This is convenient for processing analog signals: since groundreferenced voltages are located midway between the clipping limits imposed by the supply rails, the undistorted signal swing is maximized for symmetric signals such as sine waves. The situation is less pleasant in single-supply systems such as we have been considering in EE4902. With only a single supply equal to +5V, the clipping limits are approximately 0V and +5V. Therefore, for maximum signal swing, it's convenient to reference signals to a voltage at +2.5V, midway between clipping limits at the rails. This problem is concerned with the relative merits of two circuits which can be used to develop a "half-supply" voltage midway between the rails. While a resistive voltage divider might seem attractive, we will see later on in the course that (for die area and power consumption reasons) a “MOSFET-only” approach is better. Two circuits you are considering are shown as options A and B in Figure 3 on the facing page. Option A uses two N-channel devices; option B uses an N-channel and a P-channel. You may assume that the substrate (body) terminal is tied to the source terminal. You may also assume channel length modulation to be negligible (l=0) Use the following MOSFET parameters for this 2µm process AT ROOM TEMPERATURE: Parameter N-channel +1.10 5.2E-5 P-channel -1.20 1.5E-5 V A/V2 Units . Vt µCox a) In each case, find values for the device widths to meet the following requirements: VOUT = +2.5V AND ID = 100µA [10] Indicate your design values in the spaces provided underneath each option b) Now, consider how each circuit behaves in the presence of variations in threshold voltage due to variations in temperature and fabrication process. Over temperature and process variations, it is observed that the N-channel threshold voltage Vtn can vary in a range from +0.9V to +1.3V. It is also observed that the P-channel threshold voltage Vtp can vary in a range from 1.05V to -1.35V. It is further observed that these variations are independent, since the Nchannel threshold voltage Vtn and the P-channel threshold voltage Vtp are determined by separate processing steps. In the presence of temperature and supply variations, which circuit will do a better job of maintaining VOUT equal to +2.5V? Will A be better, B better, or will there be no difference? (Circle one below) [1] A BETTER NO DIFFERENCE B BETTER EXPLAIN! [9] 10 vDD = +5V M1 W1 2µm 100µA VOUT vDD = +5V M3 W3 2µm 100µA VOUT M2 W2 2µm M4 W4 2µm A Figure 3. a) W1 = _______ W2 = _______ B W3 = _______ W4 = _______ 11 4. You are attempting to design analog circuitry on a digital IC being fabricated in a CMOS process with very short gate length (L=0.18µm). The ID vs. VGS plot for a MOSFET in the active region (measured using the circuit shown in Fig. 4a) is shown below. The characteristic exhibits a "short-channel" effect: due to velocity saturation of carriers in the channel, the mobility relationship does not hold and the square law equation does not apply for predicting drain current ID. ID M1 VGS 10 0.18 VDS = +3.3V Fig. 4a. +3 mA ID +2 mA +1 mA 0 mA 0V +1V +2V VGS +3V 12 It is desired to use this MOSFET in a common-source amplifier configuration shown below, in which the small-signal input rides on a +1.5V DC bias level. vDD = +3.3V RD ID 10 0.18 vout + vin - VBIAS +1.5V a) Find the DC drain current ID at this operating point. Indicate the operating point on the ID-VGS plot. [4] ID = __________ Determine the transconductance gm at this operating point. gm = __________ b) [8] c) Determine the value of RD for an output DC bias level of +2.0V RD = __________ [4] d) Determine the small signal gain av = vout/vin of the circuit with your value of RD. You may ignore channel length modulation. [4] av = __________ 13 ...
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This note was uploaded on 10/13/2009 for the course ECE 4902 taught by Professor Mcneill during the Spring '01 term at WPI.

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