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4902C2009exam1_solutions

4902C2009exam1_solutions - Name SOLUTIONS ECE Box Average...

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Unformatted text preview: Name SOLUTIONS ECE Box # Average . Problem Score Pomts 1 23,6 24 2 l3.9 24 3 23.9 27 M 76‘ 6 4 15.2 25 0" l l .8 NET) 75‘ EE4902 C2009 Analog IC Design Exam 1 ° This is a- closed book, closed notes test! Use of calculators is OK, but no pre-stored data or formulas allowed! - The last page is a notes page which may be detached for convenience and need not be turned in with the exam - Show all your work. Partial credit may be given. If you think you need something that you can't remember, write down what you need and what you'd do if you remembered it. ° Look for the simple, straightforward way to solve the problem for the level of accuracy reguired. Don't get entangled in unnecessary algebra. . As in real life, some problems may give you more information than you need. Don‘t assume that all information must be used! It's your job to decide what's relevant to the solution. 0 You have 50 minutes to complete this exam. There are four problems on a total of 11 pages (including notes page). 1 a) Parts (a) - (c) give various MOSFET circuit configurations with the given VGS, V_DS, and threshold voltage VT“, and associated cross—sectional views of the MOSFET devrce. In each case: Indicate whether the MOSFET is an n-channel or p-channel device. In the boxes in the source, drain, and body regions write "n" or "p" to indicate whether that region is n-type or p~type silicon Sketch the distribution of mobile charge in the channel (if any), and indicate what kind of charge (holes or e~) Indicate whether the MOSFET is in the cutoff, triode, or saturation region of operation G VTH= +1.0V [8] Circle one: p-CHANNEL + VGS = +2V 11%;], Circle one: W TRIODE SATURATION V65 > VT“ V03 > VGS‘ Vm b) . [3] Circle one: n-CHANNEL Circle one: TRIODE SATURATION C) [8] Circle one: p-CHANNEL + G VTH= +1.0V B, . Circle one: CW SATURATION V65 > VT“ V053< V65 ‘Vm 2. You are evaluating a MOSFET fabricated in a 0.5ym CMOS process. The maximum power supply voltage available in the system is +5V. The test circuit shown on the opposite page is used to take the data shown in the table. VDS is held constant at +0.5V, VGS is varied from 0V to +5V over a range of values, and drain current ID is recorded in each case. v53 =asv << V55 4/1“ : TRIODE R5510“! a) D ' e the value of on resistan.ccuracy 110%) for the maximum gate drive of /" AT ng= 5V: IO =17.z MA [81 RonIVGS=+5V = szfl-l _ V03 0,5V Qom‘ _ 2 In lZZMA b) Determine the value of threshold voltage VTH (accuracy :t0.05V) for this MOSFET M [8] FROM DATA: MUST BE SOMEWHERE = 0.75 V” V BETWEEN 0.7V 4 VW 4 0.8 v 0) Determine the value of mobility ynCOX (accuracy 140%) for this MOSFET [8] mes : 4.: 5-5 A/VZ mom ram EQUA‘DoN AT 5v POINT: ' IN"? 2951,: =3>MC ~4.| E—S_— MCox 19-9 (sv—o.7sv) ox VZ 05 "D 93 : PLOT 72'— v3, V65; LOOK AT SLOPE OV‘ SLOPE : (34,4 E’3)-(8,6E'3) : 8‘33?) 5. 5V “ 1V V2 ElTHER —_'_“ .M—I. .. ONE OK Rm - ,uCax L(Vos V114) ’ W A / 8,6Ee3é % MCGX zitfh?) E157} V7— V 4 SHwLD HAVE BEEN [A] j oPaQAWo Ream»! -05 9. 68E—05 E 8 “w 1 —04 1.5 2.15E-03Ro,. |/Eon 69E 2. 1.0 30,2 8.60E—03 l l. 1. swv 2913—02 25,8 08E—02 51E—02 o m 4.5 j 3. This problem involves analysis and design of the common source amplifier circuit shown in the figure on the opposite page. You may assume that the substrate (body) terminal is tied to the source terminal. You may also assume channel length modulation to be negligible 0:0). Use the following MOSFET parameters for this process: a) Determine the value of MOSFET width W necessary to give an output DC bias point Vour = +2.5V. Numerical value required; accuracy 15% [61 w 1%: 80m 25M = .333 Ag. (1,4 — ms)Z b) In the space below, draw the low frequency small signal model for the entire circuit. [5] d Vout loom; VM J_ —— ’ c) Determine the small-signal gain vom/vin. Numerical value required; accuracy i10% [6] vow/vi, = :ZLL ~ 3m to : {20096) (100K) : - Zo d) Using the axes on the opposite page, sketch the total output vouT when vin is a 0.1V peak sine wave. Be sure to indicate numerical values for any interesting voltage levels (for example, approximate maximum and minimum values of vow). [5] e) A colleague proposes to increase the small signal gain magnitude by a factor of 2X, by doubling the resistor value RD to 200k§2 (while keeping the other design values unchanged: W, L, VBIAS). Will this work? Circle one: NO, IT ‘ WON'T WORK Explain! Why or why not? LAQGER DC VOLTAGE DROP ACROSS RD 1? MOSFET WILL CRASH INTO “FRIDGE => Vow-r WILL BE snucx NEAR ov [1] YES, IT WILL WORK [4] axes for (d): VOUT —..-..—.- A4 TYUODE CRASH? VIN: l.50\/ : V63 V6545“ : 150—- M5 = 0.35 v} Vos > Vchm SAW/{AWON / No mmoe C/eASH,’ V03 ; VOUT 2 0.5V This problem involves physical design of the load resistor for the common source amplifier from the previous problem, shown again in schematic form below. Also shown below is a view of the resistor (top view; onto the surface of the wafer). For the purposes of this problem, you may ignore the effects of contact resistance. LAYOUT (TOP VIEW) (Y DIMENSION NOT TO SCALE) VDD = +5V 100kQ Vin + ‘: y VBIAS : +1.4ov l x For the resistor, you have a choice of the following layers: Sheet resistance a) Determine the required lengths of the resistor in each material, if width of each is chosen to be WPour : NWELL = 3ym. Lpow =ili‘LO/MW‘ WELL: 7| m [6] IOOKJZ “)0ch ,_.._... = 3 846 D Y 3 :. Zédl/a flm ’760JL/a 563 D X3/um b) Which resistor material is the better choice for cost purposes? (Circle one) , [l] POLY [3] Explain!: MUCH SMALLER SILICON AREA =2) SMALLEVQ DIE => MORE DIE/WAFEQ ———> LowaQ COST/DIE 8 (1) Parts (c—e) are concerned with variation in the resistance value caused by variations in the manufacturing process. Each is example is from a separate production run, so consider each part separately. That is, the changes are not cumulative; each of parts (c—e) is concerned with only one change from the nominal process and design described in parts (a) and (b). In one production run, the wafers are left in a depostion step too long and the thickness (2 dimension) of the material in each layer is 20% greater than normal. With the thicker—than-normal layer, will the actual value of the resistance be lower, unchanged, or higher? [1] ABOUT THE SAME HIGHER (<1% CHANGE) R /O L ,J WHE R WILL BE is? vs g ~Zo% LOWER In another production run, due to a mask alignment error, all L dimensions (along the y axis) are increased by 0.5;4m. With the increased L values, will the actual value of the resistance be lower, unchanged, or higher? [1] LOWER ABOUT THE SAME HIGHER ( < 1% CHANGE ) [4] Explain!: R:/) _L__ } IF L [NCREASE‘S D N Freer/1 I7: _, 171,5, CHANGE in re 9.;— o 15 mm '7' .0,3 /0 In yet another production run, due to a mask alignment error, all W dimensions (along the x axis) are increased by 0.5}1m. fl—__. With the increased W values, will the actual value of the resistance be lower, unchanged, or higher? [1] ABOUT THE SAME HIGHER (< 1% CHANGE) [4] CHANGE?) w :2 WILL. BE ~ 47% MOSFET LARGE SIGNAL CHARACTERISTICS P CHANNEL N CHANNEL t :3 o E o SYMBOL SATURATION REGION TRIODE VDS < VGS - VTH SATURATION VDS > VGS ' VTH VGS MORE NEGATIVE I I Was MORE POSITIVE ID-VDS CHARACTERISTIC SATURATION TRIODE IVDs|>IVGs-VTH| IVDsI<IVGs-VTHI 11) SATURATION CUTOFF VGS < VTH . VGS > VTH ID-VGS CHARACTERISTIC (SATURATION REGION) CUTOFF Ves < VTH SATURATION VGS > VTH 11 ...
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