Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
IEEE ELECTRON DEVICE LETTERS, VOL. 24, NO. 5, MAY 2003 339 Performance Dependence of CMOS on Silicon Substrate Orientation for Ultrathin Oxynitride and HfO P Gate Dielectrics Min Yang, Evgeni P. Gusev, Meikei Ieong, Oleg Gluschenkov, Diane C. Boyd, Kevin K. Chan, Paul M. Kozlowski, Christopher P. D’Emic, Raymond M. Sicina, Paul C. Jamison, and Anthony I. Chou Abstract— Dependence of CMOS performance on silicon crystal orientation of (100), (111), and (110) has been investigated with the equivalent gate dielectric thickness less than 3 nm. Hole mobility enhancement of 160 7 has been observed for both oxynitride and HfO P gate dielectrics on (110) surfaces compared with (100). CMOS drive current is nearly symmetric on (110) orientation without any degradation of subthreshold slope. For HfO P gate dielectrics, an approximately 68% enhancement of pMOSFET drive current has been demonstrated on (110) substrates at poly aH IP m, while current reduction in nMOS is around 26%. Index Terms— Charge carrier mobility, inversion layers, MOSFETs. I. INTRODUCTION A N EXPONENTIAL increase in gate leakage current with decreasing gate oxide thickness is the primary motiva- tion for the recent investigations of high- materials. It has been shown that gate leakage current can be reduced by orders of magnitude with high- gate dielectrics, for example HfO and Al O [1], [2]. However, mobility degradation has been ob- served for high- gate dielectrics. It has been reported that hole mobility is much higher in MOSFETs fabricated on (110) or (111) substrates with conventional SiO [3]–[8], which may be an opportunity for devices with high- gate dielectrics to be able to minimize the negative effect on the carrier mobility. While novel structures, for example, finFET [9] and vertical MOSFETs [10], [11], enable the device channel to be fabricated on various crystal orientations, CMOS fabrication on (110) or (111) orientation has traditionally been hampered by their in- ferior gate oxide reliability; although, it was recently reported that gate oxide quality is actually slightly better on (111) sub- strate in the direct tunneling regime [7]. With different growth techniques (chemical vapor deposition versus oxidation), less crystal orientation dependence of gate dielectric reliability is ex- pected for some high- gate dielectrics. As such, CMOS with Manuscript received January 22, 2003. The review of this letter was arranged by Editor B. Yu. M. Yang, E. P. Gusev, K. K. Chan, P. M. Kozlowski, C. P. D’Emic, and R. M. Sicina are with the IBM Semiconductor Research and Development Center (SRDC), Research Division, T. J. Watson Research Center, Yorktown Heights, NY 10598 USA. M. Ieong, O. Gluschenkov, D. C. Boyd, P. C. Jamison, and A. I. Chou are with the IBM Semiconductor Research and Development Center (SRDC), Mi- croelectronics Division, Hopewell Junction, NY 12533 USA. Digital Object Identifier 10.1109/LED.2003.812565
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 10/13/2009 for the course ECE 3901 taught by Professor Aboud during the Spring '09 term at WPI.

Page1 / 3


This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online