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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 49, NO. 2, FEBRUARY 2002 279 Design and Fabrication of 50-nm Thin-Body p-MOSFETs With a SiGe Heterostructure Channel Yee-Chia Yeo , Student Member, IEEE , Vivek Subramanian , Member, IEEE , Jakub Kedzierski, Peiqi Xuan, Tsu-Jae King , Senior Member, IEEE , Jeffrey Bokor , Fellow, IEEE , and Chenming Hu , Fellow, IEEE Abstract— Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short- channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorpo- ration of Si H U Ge H Q in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure- channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel. Index Terms— Heterojunctions, MOSFETs, SiGe, strain, thin- body. I. INTRODUCTION A S the gate length of the MOSFET is scaled down into the sub-100-nm regime for improved performance and density, the requirements for body-doping concentration, gate oxide thickness, and source/drain (S/D) doping profiles to control short-channel effects become increasingly difficult to meet when conventional device structures based on bulk sil- icon (Si) substrates are employed. The heavy channel doping re- quired to provide adequate suppression of short-channel effects results in degraded mobility and enhanced junction leakage. The aggressive reduction of the SiO gate dielectric thickness for reduced short-channel effects and improved drive current leads to increased direct tunneling gate leakage current and standby power consumption, and also raises concerns regarding the gate oxide reliability. For device scaling well into the sub-100-nm regime, a promising approach to controlling short-channel ef- fects is to use a thin Si film as the MOSFET channel so that sub-surface leakage paths are eliminated. A device structure that implements this concept is the thin-body MOSFET [1], [2]. In a thin-body MOSFET, the source-to-drain current is restricted to flow in a region close to the gate for superior gate control, as illustrated in Fig. 1. Since it does not rely on a heavily-doped channel for the suppression of short-channel effects, it avoids the problems of mobility degradation due to impurity scattering and threshold voltage fluctuation due to the random vari- Manuscript received July 13, 2001; revised October 31, 2001. This work was supported by DARPA ETO-AME under Contract N66001-97-1-8910. Y.-C. Yeo acknowledges fellowship support from NUS, Singapore. The review of this
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This note was uploaded on 10/13/2009 for the course ECE 3901 taught by Professor Aboud during the Spring '09 term at WPI.

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