Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 10, OCTOBER 2003 2095 Scaling Fully Depleted SOI CMOS Vishal P. Trivedi , Student Member, IEEE, and Jerry G. Fossum , Fellow, IEEE Abstract— Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are done to examine the scalability and perfor- mance potential of the technology. The quasi-2-D analyses, which can apply to double-gate devices as well, also provide a simple expression to estimate the effective channel length ( e ) of FD/SOI MOSFETs. The insightful results show that threshold-voltage control via channel doping and polysilicon gates is not a viable option for extremely scaled FD/SOI CMOS, and hence that undoped channels and metal gate(s) with tuned work function(s) must be employed. Quantitative as well as qualitative insights gained on the short-channel effects reveal the need for ultrathin films ( Si IH nm) for e SH nm. However, the implied manufacturing burden, compounded by effects of carrier-energy quantization for ultrathin Si , forces a pragmatic limit on Si of about 5 nm, which in turn limits the scalability to e aPS QH nm. Unloaded CMOS-inverter ring-oscillator simulations, done with our process/physics-based compact model (UFDG) in SPICE3, show very good performance for e aQS nm, and suggest viable technology designs for low-power as well as high-performance applications. These simulations also reveal that moderate variations in Si can be tolerated, and that the energy quantization significantly influences the scaled-technology performance and hence must be properly accounted for in optimal FD/SOI MOSFET design. Index Terms— Energy quantization, FD/SOI CMOS, MOSFET scaling, short-channel effects, threshold voltage. I. INTRODUCTION C ONVENTIONAL, fully depleted (FD) silicon-on-insultor (SOI) CMOS, the device structure of which is illustrated in Fig. 1, was of much interest a decade ago because of its pro- jected superiority over the partially depleted and the bulk-silicon (Si) counterparts [1]. Its advantages, due mainly to the (front) gate-substrate charge coupling enabled by the thin FD Si-film body on a thick buried oxide (BOX) [2], [3], included higher drive current/transconductance, near-ideal subthreshold slope, and suppression of the floating-body effects. However, in the deep sub-micron regime, these advantages diminished [3], and the interest in FD/SOI CMOS subsided. Now, as CMOS technology is being rapidly scaled [4], increases in junction tunneling currents and the dependence of PD/SOI and bulk-Si CMOS on precise channel doping densities and gradients to control the short-channel effects (SCEs) [5] imply that neither technology can be scaled to the end of the Semiconductor Industry Association (SIA) International Technology Roadmap for Semiconductors (ITRS) [4], i.e., to Manuscript received February 11, 2003; revised July 8, 2003. This work was
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
Image of page 2
This is the end of the preview. Sign up to access the rest of the document.

This note was uploaded on 10/13/2009 for the course ECE 3901 taught by Professor Aboud during the Spring '09 term at WPI.

Page1 / 9


This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online