lecnew-16-SPIEx

lecnew-16-SPIEx - WPI ECE2801 Foundations of Embedded...

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Unformatted text preview: WPI ECE2801 Foundations of Embedded Computer Systems Lecture 16: SPI Examples EE2801: Foundations of Embedded Systems Lecture 16 Review Parallel interfaces vs. Serial Interfaces Parallel interfaces: transmit multiple bits at one time one connection per bit; Primarily used to connect devices on the same IC or on the same circuit board. Serial interfaces: Transmit one bit at one time a single data wire; commonly used for off-chip communications; need interfacing logic and communication protocol. Asynchronous vs. Synchronous communications Share or not share clock Asynchronous: extra control signals, such as read and write signals, are eliminated; character timing information is recovered from the data stream, using designated "start" and "stop" bits to indicate the framing of each character. Synchronous: master/slave mode, master device provides clock signal. USART: Serial interface Asynchronous mode: UART Synchronous mode: SPI EE2801: Foundations of Embedded Systems Lecture 16 SPI mode Synchronous/Serial Peripheral Interface Bus (SPI) Used primarily for synchronous serial communications between a CPU and peripherals within the box Synchronous = shared clock Master/Slave mode: Master provides the clock Usually a 4 wire connection (some times 3 wire) SIMO = Slave In/Master Out data line SOMI = Slave Out/ Master In data SCLK = Serial Clock (UCLK in MSP430 USART) CS = Chip Select (STE: Slave Transmit Enable in MSP430 USART) EE2801: Foundations of Embedded Systems Lecture 16 USART Registers: SPI mode USART1 has the same set of control and status registers. EE2801: Foundations of Embedded Systems Lecture 16 USART Control Register (UxCTL) I2C mode or SPI mode. Character length ( CHAR , 7-bit data or 8-bit data) Loopback mode (LISTEN=1) SYNC selects UART mode or SPI mode (SYNC=1SPI) MM selects Master mode or slave mode SWRST : Software reset enable EE2801: Foundations of Embedded Systems Lecture 16 USART Transmit Control Register (UxTCTL) BRCLK source select ( SSELx ) STC: Slave transmit select STC=0 STE enabled STC=1 STE disabled Other features such as clock phase select (CKPH), clock polarity select (CKPL), transmitter empty flag (TXEPT) EE2801: Foundations of Embedded Systems Lecture 16 USART Receive Control Register (UxRCTL) Error flags to indicate receiving status: error or no error Framing error flag (FE) Overrun error flag (OE) EE2801: Foundations of Embedded Systems...
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This note was uploaded on 10/12/2009 for the course ECE 2801 taught by Professor Jarvis during the Spring '08 term at WPI.

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lecnew-16-SPIEx - WPI ECE2801 Foundations of Embedded...

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