ca3046

ca3046 - CA3045, CA3046 Data Sheet September 1998 File...

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1 CA3045, CA3046 General Purpose NPN Transistor Arrays The CA3045 and CA3046 each consist of five general purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially connected pair. The transistors of the CA3045 and CA3046 are well suited to a wide variety of applications in low power systems in the DC through VHF range. They may be used as discrete transistors in conventional circuits. However, in addition, they provide the very significant inherent integrated circuit advantages of close electrical and thermal matching. Pinout CA3045, (CERDIP) CA3046 (PDIP, SOIC) TOP VIEW Features • Two Matched Transistors -V BE Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5mV -I IO Match. . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 µ A (Max) • Low Noise Figure . . . . . . . . . . . . . . . . 3.2dB (Typ) at 1kHz • 5 General Purpose Monolithic Transistors • Operation From DC to 120MHz • Wide Operating Current Range • Full Military Temperature Range Applications • Three Isolated Transistors and One Differentially Connected Transistor Pair for Low Power Applications at Frequencies from DC Through the VHF Range • Custom Designed Differential Amplifiers • Temperature Compensated Amplifiers • See Application Note, AN5296 “Application of the CA3018 Integrated-Circuit Transistor Array” for Suggested Applications Ordering Information PART NUMBER (BRAND) TEMP. RANGE ( o C) PACKAGE PKG. NO. CA3045F -55 to 125 14 Ld CERDIP F14.3 CA3046 -55 to 125 14 Ld PDIP E14.3 CA3046M (3046) -55 to 125 14 Ld SOIC M14.15 CA3046M96 (3046) -55 to 125 14 Ld SOIC Tape and Reel M14.15 SUBSTRATE 1 2 3 4 5 6 7 14 13 12 11 10 9 8 DIFFERENTIAL PAIR Q 1 Q 5 Q 4 Q 3 Q 2 Data Sheet September 1998 File Number 341.4 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
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2 Absolute Maximum Ratings Thermal Information Collector-to-Emitter Voltage (V CEO ) . . . . . . . . . . . . . . . . . . . . . 15V Collector-to-Base Voltage (V CBO ) . . . . . . . . . . . . . . . . . . . . . . . 20V Collector-to-Substrate Voltage (V CIO , Note 1) . . . . . . . . . . . . . . 20V Emitter-to-Base Voltage (V EBO ) . . . . . . . . . . . . . . . . . . . . . . . . . 5V Collector Current (I C ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55 o C to 125 o C Thermal Resistance (Typical, Note 2) θ JA ( o C/W) θ JC ( o C/W) PDIP Package . . . . . . . . . . . . . . . . . . . 180 N/A CERDIP Package. . . . . . . . . . . . . . . . . 150 75 SOIC Package . . . . . . . . . . . . . . . . . . . 220 N/A Maximum Power Dissipation (Any One Transistor) . . . . . . . 300mW Maximum Junction Temperature (Hermetic Packages). . . . . . . .175 o C Maximum Junction Temperature (Plastic Package) . . . . . . . .150 o C Maximum Storage Temperature Range. . . . . . . . . . -65 o C to 150 o C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300 o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
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ca3046 - CA3045, CA3046 Data Sheet September 1998 File...

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