iceconomics

iceconomics - Lect u re Overview IC Fabrication: Silicon...

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w e i v r e v O e r u t c e L s o e d i v I I / I n u R n o c i l i S : n o i t a c i r b a F C I w o l F s s e c o r P s e u s s I c i m o n o c E
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Process Flow WAFER FABRICATION WAFER TEST SCRIBE & PACKAGE FINAL TEST COST: Cw (PER WAFER) N Y 2 Y 1 N Y 1 N YIELD: Y1 (FRACTION PASSING TEST 1) COST: Cp (PER DIE) YIELD: Y2 (FRACTION PASSING TEST 2) FAIL TEST 1 FAIL TEST 1 A WAFER A DIE N N: Gross die per wafer Y 2 Y 1 N = N G : Good die per wafer
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Cost per Die Total Cost Total number of good die Cost per good die Benefits of Smaller Chip Area More die per wafer (higher N) Higher Yield CY N C WP + 1 YY N 12 N C C C Y W WAFER FAB P PACKAGE + =+ 1 2 123 {
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Smaller Die Size: Higher Yield POINT DEFECTS RANDOMLY DISTRIBUTED OVER WAFER N = 13 die 6 good Y = 6/13 = 46% N = 68 60 good Y = 60/68 = 88%
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Example: Yield vs. die size DIE SIZE YIELD (%) 100 10 1 30 20 50 70 3 2 5 7 10 20 30 40 50
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Example Process: 20cm diameter wafer Wafer cost: C W = $4000 per wafer Package cost: C P = $1.70 per package Final test yield: Y 2 = 0.95 A DIE =40mm 2
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This note was uploaded on 10/13/2009 for the course ECE 4902 taught by Professor Mcneill during the Spring '01 term at WPI.

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iceconomics - Lect u re Overview IC Fabrication: Silicon...

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