74-373 - DM54LS373 DM74LS373 DM54LS374 DM74LS374 TRI-STATE...

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TL/F/6431 DM54LS373/DM74LS373, DM54LS374/DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops May 1992 DM54LS373/DM74LS373, DM54LS374/DM74LS374 TRI-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops General Description These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relative- ly low-impedance loads. The high-impedance state and in- creased high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for inter- face or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. (Continued) Features Y Choice of 8 latches or 8 D-type flip-flops in a single package Y TRI-STATE bus-driving outputs Y Full parallel-access for loading Y Buffered control inputs Y P-N-P inputs reduce D-C loading on data lines Connection Diagrams Dual-In-Line Packages ’LS373 TL/F/6431–1 Order Number DM54LS373J, DM54LS373W, DM74LS373N or DM74LS373WM See NS Package Number J20A, M20B, N20A or W20A ’LS374 TL/F/6431–2 Order Number DM54LS374J, DM54LS374W, DM74LS374WM or DM74LS374N See NS Package Number J20A, M20B, N20A or W20A TRI-STATE is a registered trademark of National Semiconductor Corp. C 1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.
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General Description (Continued) The eight latches of the DM54/74LS373 are transparent D- type latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was set up. The eight flip-flops of the DM54/74LS374 are edge-trig- gered D-type flip flops. On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines signifi- cantly. The output control does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered even while the outputs are off. Function Tables DM54/74LS373 Output Enable D Output Control G L H H H L H L L L L X Q 0 H X X Z DM54/74LS374 Output Clock D Output Control L u H H L u L L L L X Q 0 H X X Z H e High Level (Steady State), L e Low Level (Steady State), X e Don’t Care u e Transition from low-to-high level, Z e High Impedance State Q 0 e The level of the output before steady-state input conditions were established.
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