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Unformatted text preview: © 2000 Fairchild Semiconductor Corporation DS008442 www.fairchildsemi.com August 1986 Revised March 2000 DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver DM74LS244 Octal 3-STATE Buffer/Line Driver/Line Receiver General Description These buffers/line drivers are designed to improve both the performance and PC board density of 3-STATE buffers/ drivers employed as memory-address drivers, clock driv- ers, and bus-oriented transmitters/receivers. Featuring 400 mV of hysteresis at each low current PNP data line input, they provide improved noise rejection and high fanout out- puts and can be used to drive terminated lines down to 133 Ω . Features ■ 3-STATE outputs drive bus lines directly ■ PNP inputs reduce DC loading on bus lines ■ Hysteresis at data inputs improves noise margins ■ Typical I OL (sink current) 24 mA ■ Typical I OH (source current)- 15 mA ■ Typical propagation delay times Inverting 10.5 ns Noninverting 12 ns ■ Typical enable/disable time 18 ns ■ Typical power dissipation (enabled) Inverting 130 mW Noninverting 135 mW Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table L = LOW Logic Level H = HIGH Logic Level X = Either LOW or HIGH Logic Level Z = High Impedance Order Number Package Number Package Description DM74LS244WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS244SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5....
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This note was uploaded on 10/16/2009 for the course EL el6303 taught by Professor Prof during the Spring '09 term at NYU Poly.
- Spring '09