lec0Fab - Introduction to CMOS VLSI Design Layout,...

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Introduction to CMOS VLSI Design Layout, Fabrication, and Elementary Logic Design
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Fabrication and Layout Slide 2 CMOS VLSI Design Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): very many Metal Oxide Semiconductor (MOS) transistor Fast, cheap, low-power transistors Complementary: mixture of n- and p-type leads to less power Today: How to build your own simple CMOS chip CMOS transistors Building logic gates from transistors Transistor layout and fabrication Rest of the course: How to build a good CMOS chip
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Fabrication and Layout Slide 3 CMOS VLSI Design Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors Si Si Si Si Si Si Si Si Si
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Fabrication and Layout Slide 4 CMOS VLSI Design Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) As Si Si Si Si Si Si Si Si B Si Si Si Si Si Si Si Si - + + -
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Fabrication and Layout Slide 5 CMOS VLSI Design p-n Junctions A junction between p-type and n-type semiconductor forms a diode. Current flows only in one direction p-type n-type anode cathode
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Fabrication and Layout Slide 6 CMOS VLSI Design nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor Gate and body are conductors – SiO 2 (oxide) is a very good insulator Called metal – oxide – semiconductor (MOS) capacitor Even though gate is no longer made of metal n+ p Gate Source Drain bulk Si SiO 2 Polysilicon n+
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Fabrication and Layout Slide 7 CMOS VLSI Design nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF n+ p Gate Source Drain bulk Si SiO 2 Polysilicon n+ D 0 S
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Fabrication and Layout Slide 8 CMOS VLSI Design nMOS Operation When the gate is at a high voltage: Positive charge on gate of MOS capacitor Negative charge attracted to body Inverts a channel under gate to n-type Now current can flow through n-type silicon from source through channel to drain, transistor is ON n+ p Gate Source Drain bulk Si SiO 2 Polysilicon n+ D 1 S
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Fabrication and Layout Slide 9 CMOS VLSI Design pMOS Transistor Similar, but doping and voltages reversed – Body tied to high voltage (V DD ) Gate low: transistor ON Gate high: transistor OFF Bubble indicates inverted behavior SiO 2 n Gate Source Drain bulk Si Polysilicon p+ p+
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lec0Fab - Introduction to CMOS VLSI Design Layout,...

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