lec5LogicalEffort - Introduction to CMOS VLSI Design...

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Introduction to CMOS VLSI Design Logical Effort
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Logical Effort Slide 2 CMOS VLSI Design Outline Introduction Delay in a Logic Gate Multistage Logic Networks Choosing the Best Number of Stages Example Summary
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Logical Effort Slide 3 CMOS VLSI Design Introduction Chip designers face a bewildering array of choices What is the best circuit topology for a function? How many stages of logic give least delay? How wide should the transistors be? Logical effort is a method to make these decisions Uses a simple model of delay Allows back-of-the-envelope calculations Helps make rapid comparisons between alternatives Emphasizes remarkable symmetries ? ? ?
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Logical Effort Slide 4 CMOS VLSI Design Example Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. Decoder specifications: 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementary address inputs A[3:0] Each input may drive 10 unit-sized transistors Ben needs to decide: How many stages to use? How large should each gate be? How fast can decoder operate? A[3:0] A[3:0] 16 32 bits 16 words 4:16 Decoder Register File
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Logical Effort Slide 5 CMOS VLSI Design Delay in a Logic Gate Express delays in process-independent unit abs d d τ = τ = 3RC 12 ps in 180 nm process 40 ps in 0.6 μ m process
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Logical Effort Slide 6 CMOS VLSI Design Delay in a Logic Gate Express delays in process-independent unit Delay has two components abs d d τ = d f p = +
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Logical Effort Slide 7 CMOS VLSI Design Delay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f = gh (a.k.a. stage effort ) Again has two components abs d d τ = d p f = +
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Logical Effort Slide 8 CMOS VLSI Design Delay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f = g h (a.k.a. stage effort) Again has two components g : logical effort Measures relative ability of gate to deliver current g 1 for inverter abs d d τ = d f p = +
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Logical Effort Slide 9 CMOS VLSI Design Delay in a Logic Gate Express delays in process-independent unit Delay has two components Effort delay f = g h (a.k.a. stage effort) Again has two components h : electrical effort = C out / C in Ratio of output to input capacitance Sometimes called fanout abs d d τ = d f p = +
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Logical Effort Slide 10 CMOS VLSI Design Delay in a Logic Gate Express delays in process-independent unit Delay has two components Parasitic delay p Represents delay of gate driving no load Set by internal parasitic capacitance abs d d τ = d p f = +
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Logical Effort Slide 11 CMOS VLSI Design Delay Plots d = f + p = gh + p Electrical Effort: h = C out / C in Normalized Delay: d Inverter 2-input NAND g = p = d = g = p = d = 0 1 2 3 4 5 0 1 2 3 4 5 6
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This note was uploaded on 10/13/2009 for the course ECE 482 taught by Professor Adnanaziz during the Spring '07 term at University of Texas at Austin.

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lec5LogicalEffort - Introduction to CMOS VLSI Design...

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