{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

lec6Interconnect - Introduction to CMOS VLSI Design...

Info icon This preview shows pages 1–13. Sign up to view the full content.

View Full Document Right Arrow Icon
Introduction to CMOS VLSI Design Interconnect
Image of page 1

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Interconnect Slide 2 CMOS VLSI Design Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters
Image of page 2
Interconnect Slide 3 CMOS VLSI Design Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally
Image of page 3

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Interconnect Slide 4 CMOS VLSI Design Wire Geometry Pitch = w + s Aspect ratio: AR = t/w Old processes had AR << 1 Modern processes have AR 2 Pack in many skinny wires l w s t h
Image of page 4
Interconnect Slide 5 CMOS VLSI Design Layer Stack AMI 0.6 μ m process has 3 metal layers Modern processes use 6-10+ metal layers Example: Intel 180 nm process M1: thin, narrow (< 3 λ ) High density cells M2-M4: thicker For longer wires M5-M6: thickest For V DD , GND, clk Layer T (nm) W (nm) S (nm) AR 6 1720 860 860 2.0 1000 5 1600 800 800 2.0 1000 4 1080 540 540 2.0 700 3 700 320 320 2.2 700 2 700 320 320 2.2 700 1 480 250 250 1.9 800 Substrate
Image of page 5

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Interconnect Slide 6 CMOS VLSI Design Wire Resistance ρ = resistivity ( *m) l w t R =
Image of page 6
Interconnect Slide 7 CMOS VLSI Design Wire Resistance ρ = resistivity ( *m) l w t l R t w ρ =
Image of page 7

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Interconnect Slide 8 CMOS VLSI Design Wire Resistance ρ = resistivity ( *m) R = sheet resistance ( / ) n is a dimensionless unit(!) Count number of squares R = R * (# of squares) l w t 1 Rectangular Block R = R (L/W) 4 Rectangular Blocks R = R (2L/2W) = R (L/W) t l w w l l l R R t w w ρ = = W
Image of page 8
Interconnect Slide 9 CMOS VLSI Design Choice of Metals Until 180 nm generation, most wires were aluminum Modern processes often use copper Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier Metal Bulk resistivity ( μ Ω *cm) Silver (Ag) 1.6 Copper (Cu) 1.7 Gold (Au) 2.2 Aluminum (Al) 2.8 Tungsten (W) 5.3 Molybdenum (Mo) 5.3
Image of page 9

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Interconnect Slide 10 CMOS VLSI Design Sheet Resistance Typical sheet resistances in 180 nm process Layer Sheet Resistance ( / ) Diffusion (silicided) 3-10 Diffusion (no silicide) 50-200 Polysilicon (silicided) 3-10 Polysilicon (no silicide) 50-400 Metal1 0.08 Metal2 0.05 Metal3 0.05 Metal4 0.03 Metal5 0.02 Metal6 0.02
Image of page 10
Interconnect Slide 11 CMOS VLSI Design Contacts Resistance Contacts and vias also have 2-20 Use many contacts for lower R Many small contacts for current crowding around periphery
Image of page 11

Info icon This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Interconnect Slide 12 CMOS VLSI Design Wire Capacitance
Image of page 12
Image of page 13
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

What students are saying

  • Left Quote Icon

    As a current student on this bumpy collegiate pathway, I stumbled upon Course Hero, where I can find study resources for nearly all my courses, get online help from tutors 24/7, and even share my old projects, papers, and lecture notes with other students.

    Student Picture

    Kiran Temple University Fox School of Business ‘17, Course Hero Intern

  • Left Quote Icon

    I cannot even describe how much Course Hero helped me this summer. It’s truly become something I can always rely on and help me. In the end, I was not only able to survive summer classes, but I was able to thrive thanks to Course Hero.

    Student Picture

    Dana University of Pennsylvania ‘17, Course Hero Intern

  • Left Quote Icon

    The ability to access any university’s resources through Course Hero proved invaluable in my case. I was behind on Tulane coursework and actually used UCLA’s materials to help me move forward and get everything together on time.

    Student Picture

    Jill Tulane University ‘16, Course Hero Intern