lec6Interconnect - Introduction to CMOS VLSI Design...

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Introduction to CMOS VLSI Design Interconnect
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Interconnect Slide 2 CMOS VLSI Design Outline Introduction Wire Resistance Wire Capacitance Wire RC Delay Crosstalk Wire Engineering Repeaters
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Interconnect Slide 3 CMOS VLSI Design Introduction Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires Wires are as important as transistors Speed Power Noise Alternating layers run orthogonally
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Interconnect Slide 4 CMOS VLSI Design Wire Geometry Pitch = w + s Aspect ratio: AR = t/w Old processes had AR << 1 Modern processes have AR 2 Pack in many skinny wires l w s t h
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Interconnect Slide 5 CMOS VLSI Design Layer Stack AMI 0.6 μ m process has 3 metal layers Modern processes use 6-10+ metal layers Example: Intel 180 nm process M1: thin, narrow (< 3 λ ) High density cells M2-M4: thicker For longer wires M5-M6: thickest – For V DD , GND, clk Layer T (nm) W (nm) S (nm) AR 6 1720 860 860 2.0 1000 5 1600 800 800 2.0 1000 4 1080 540 540 2.0 700 3 700 320 320 2.2 700 2 700 320 320 2.2 700 1 480 250 250 1.9 800 Substrate
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Interconnect Slide 6 CMOS VLSI Design Wire Resistance ρ = resistivity ( *m) l w t R =
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Interconnect Slide 7 CMOS VLSI Design Wire Resistance ρ = resistivity ( *m) l w t l R t w ρ =
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Interconnect Slide 8 CMOS VLSI Design Wire Resistance ρ = resistivity ( *m) R = sheet resistance ( / ) n is a dimensionless unit(!) Count number of squares – R = R * (# of squares) l w t 1 Rectangular Block R = R (L/W) 4 Rectangular Blocks R = R (2L/2W) = R (L/W) t l w w l l l R R t w w ρ = = W
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Interconnect Slide 9 CMOS VLSI Design Choice of Metals Until 180 nm generation, most wires were aluminum Modern processes often use copper Cu atoms diffuse into silicon and damage FETs Must be surrounded by a diffusion barrier Metal Bulk resistivity ( μ Ω *cm) Silver (Ag) 1.6 Copper (Cu) 1.7 Gold (Au) 2.2 Aluminum (Al) 2.8 Tungsten (W) 5.3 Molybdenum (Mo) 5.3
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Interconnect Slide 10 CMOS VLSI Design Sheet Resistance Typical sheet resistances in 180 nm process Layer Sheet Resistance ( / ) Diffusion (silicided) 3-10 Diffusion (no silicide) 50-200 Polysilicon (silicided) 3-10 Polysilicon (no silicide) 50-400 Metal1 0.08 Metal2 0.05 Metal3 0.05 Metal4 0.03 Metal5 0.02 Metal6 0.02
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Interconnect Slide 11 CMOS VLSI Design Contacts Resistance Contacts and vias also have 2-20 Use many contacts for lower R Many small contacts for current crowding around periphery
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lec6Interconnect - Introduction to CMOS VLSI Design...

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