lec8CombCcts - Introduction to CMOS VLSI Design...

Info iconThis preview shows pages 1–13. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Introduction to CMOS VLSI Design Combinational Circuits Combinational Circuits Slide 2 CMOS VLSI Design Outline Bubble Pushing Compound Gates Logical Effort Example Input Ordering Asymmetric Gates Skewed Gates Best P/N ratio Combinational Circuits Slide 3 CMOS VLSI Design Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. Combinational Circuits Slide 4 CMOS VLSI Design Example 1 module mux(input s, d0, d1, output y); assign y = s ? d1 : d0; endmodule 1) Sketch a design using AND, OR, and NOT gates. D0 S D1 S Y Combinational Circuits Slide 5 CMOS VLSI Design Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. Combinational Circuits Slide 6 CMOS VLSI Design Example 2 2) Sketch a design using NAND, NOR, and NOT gates. Assume ~S is available. Y D0 S D1 S Combinational Circuits Slide 7 CMOS VLSI Design Bubble Pushing Start with network of AND / OR gates Convert to NAND / NOR + inverters Push bubbles around to simplify logic – Remember DeMorgan’s Law Y Y Y D Y (a) (b) (c) (d) Combinational Circuits Slide 8 CMOS VLSI Design Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. Combinational Circuits Slide 9 CMOS VLSI Design Example 3 3) Sketch a design using one compound gate and one NOT gate. Assume ~S is available. Y D0 S D1 S Combinational Circuits Slide 10 CMOS VLSI Design Compound Gates Logical Effort of compound gates A B C D Y A B C Y A B C C A B A B C D A C B D 2 2 1 4 4 4 2 2 2 2 4 4 4 4 g A = 6/3 g B = 6/3 g C = 5/3 p = 7/3 g A = g B = g C = p = g D = Y A A Y g A = 3/3 p = 3/3 2 1 Y Y unit inverter AOI21 AOI22 A C D E Y B Y B C A D E A B C D E g A = g B = g C = g D = 2 2 2 2 2 6 6 6 6 3 p = g E = Complex AOI Y A B C = + g Y A B C D = + g g ( 29 Y A B C D E = + + g g Y A = Combinational Circuits Slide 11 CMOS VLSI Design Compound Gates Logical Effort of compound gates A B C D Y A B C Y A B C C A B A B C D A C B D 2 2 1 4 4 4 2 2 2 2 4 4 4 4 g A = 6/3 g B = 6/3 g C = 5/3 p = 7/3 g A = 6/3 g B = 6/3 g C = 6/3 p = 12/3 g D = 6/3 Y A A Y g A = 3/3 p = 3/3 2 1 Y Y unit inverter AOI21 AOI22 A C D E Y B Y B C A D E A B C D E g A = 5/3 g B = 8/3 g C = 8/3 g D = 8/3 2 2 2 2 2 6 6 6 6 3 p = 16/3 g E = 8/3 Complex AOI Y A B C = + g Y A B C D = + g g ( 29 Y A B C D E = + + g g Y A = Combinational Circuits Slide 12...
View Full Document

This note was uploaded on 10/13/2009 for the course ECE 482 taught by Professor Adnanaziz during the Spring '07 term at University of Texas at Austin.

Page1 / 37

lec8CombCcts - Introduction to CMOS VLSI Design...

This preview shows document pages 1 - 13. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online