lec10SeqElts - Introduction to CMOS VLSI Design Sequential...

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Introduction to CMOS VLSI Design Sequential Circuits
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Sequential Logic Slide 2 CMOS VLSI Design Outline Sequencing Sequencing Element Design Max and Min-Delay Clock Skew Time Borrowing Two-Phase Clocking
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Sequential Logic Slide 3 CMOS VLSI Design Sequencing Combinational logic output depends on current inputs Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline CL clk in out clk clk clk CL CL Pipeline Finite State Machine
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Sequential Logic Slide 4 CMOS VLSI Design Sequencing Cont. If tokens moved through pipeline at constant speed, no sequencing elements would be necessary Ex: fiber-optic cable Light pulses (tokens) are sent down cable Next pulse sent before first reaches end of cable No need for hardware to separate pulses But dispersion sets min time between pulses This is called wave pipelining in circuits In most circuits, dispersion is high Delay fast tokens so they don’t catch slow ones.
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Sequential Logic Slide 5 CMOS VLSI Design Sequencing Overhead Use flip-flops to delay fast tokens so they move through exactly one stage each cycle. Inevitably adds some delay to the slow tokens Makes circuit slower than just the logic delay Called sequencing overhead Some people call this clocking overhead But it applies to asynchronous circuits too Inevitable side effect of maintaining sequence
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Sequential Logic Slide 6 CMOS VLSI Design Sequencing Elements Latch : Level sensitive a.k.a. transparent latch, D latch Flip-flop : edge triggered A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams Transparent Opaque Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop)
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Sequential Logic Slide 7 CMOS VLSI Design Sequencing Elements Latch : Level sensitive a.k.a. transparent latch, D latch Flip-flop : edge triggered A.k.a. master-slave flip-flop, D flip-flop, D register Timing Diagrams Transparent Opaque Edge-trigger D Flop Latch Q clk clk D Q clk D Q (latch) Q (flop)
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Sequential Logic Slide 8 CMOS VLSI Design Latch Design Pass Transistor Latch Pros + + Cons D Q φ
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Sequential Logic Slide 9 CMOS VLSI Design Latch Design Pass Transistor Latch Pros + Tiny + Low clock load Cons – V t drop nonrestoring backdriving output noise sensitivity dynamic diffusion input D Q φ Used in 1970’s
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Sequential Logic Slide 10 CMOS VLSI Design Latch Design Transmission gate + - D Q φ φ
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Sequential Logic Slide 11 CMOS VLSI Design Latch Design Transmission gate + No V t drop - Requires inverted clock D Q φ φ
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This note was uploaded on 10/13/2009 for the course ECE 482 taught by Professor Adnanaziz during the Spring '07 term at University of Texas at Austin.

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lec10SeqElts - Introduction to CMOS VLSI Design Sequential...

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