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Unformatted text preview: Introduction to CMOS VLSI Design Design for Low Power Design for Low Power Slide 2 CMOS VLSI Design Outline Power and Energy Dynamic Power Static Power Low Power Design Design for Low Power Slide 3 CMOS VLSI Design Power and Energy Power is drawn from a voltage source attached to the V DD pin(s) of a chip. Instantaneous Power: Energy: Average Power: ( ) ( ) DD DD P t i t V = ( ) ( ) T T DD DD E P t dt i t V dt = = avg 1 ( ) T DD DD E P i t V dt T T = = Design for Low Power Slide 4 CMOS VLSI Design Dynamic Power Dynamic power is required to charge and discharge load capacitances when transistors switch. One cycle involves a rising and falling output. On rising output, charge Q = CV DD is required On falling output, charge is dumped to GND This repeats Tf sw times over an interval of T C f sw i DD (t) VDD Design for Low Power Slide 5 CMOS VLSI Design Dynamic Power Cont. C f sw i DD (t) VDD dynamic P = Design for Low Power Slide 6 CMOS VLSI Design Dynamic Power Cont. C f sw i DD (t) VDD [ ] dynamic sw 2 sw 1 ( ) ( ) T DD DD T DD DD DD DD DD P i t V dt T V i t dt T V Tf CV T CV f = = = = Design for Low Power Slide 7 CMOS VLSI Design Activity Factor Suppose the system clock frequency = f Let f sw = f, where = activity factor If the signal is a clock, = 1 If the signal switches once per cycle, = Dynamic gates: Switch either 0 or 2 times per cycle, = Static gates: Depends on design, but typically = 0.1 Dynamic power: 2 dynamic DD P CV f = Design for Low Power Slide 8 CMOS VLSI Design Short Circuit Current...
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This note was uploaded on 10/13/2009 for the course ECE 482 taught by Professor Adnanaziz during the Spring '07 term at University of Texas at Austin.
 Spring '07
 AdnanAziz
 Volt

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