lec13SRAM - Introduction to CMOS VLSI Design SRAM Outline...

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Introduction to CMOS VLSI Design SRAM
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SRAM Slide 2 CMOS VLSI Design Outline Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Serial Access Memories
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SRAM Slide 3 CMOS VLSI Design Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Static RAM (SRAM) Dynamic RAM (DRAM) Shift Registers Queues First In First Out (FIFO) Last In First Out (LIFO) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM
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SRAM Slide 4 CMOS VLSI Design Array Architecture 2 n words of 2 m bits each If n >> m, fold by 2 k into fewer rows of more columns Good regularity – easy to design Very high density if good cells are used row decoder column decoder n n-k k 2 m bits column circuitry bitline conditioning memory cells: 2 n-k rows x 2 m+k columns bitlines wordlines
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SRAM Slide 5 CMOS VLSI Design 12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 λ unit cell bit write write_b read read_b
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SRAM Slide 6 CMOS VLSI Design 6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: Precharge bit, bit_b Raise wordline Write: Drive data onto bit, bit_b Raise wordline bit bit_b word
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SRAM Slide 7 CMOS VLSI Design SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip bit bit_b N1 N2 P1 A P2 N3 N4 A_b word 0.0 0.5 1.0 1.5 0 100 200 300 400 500 600 time (ps) word bit A A_b bit_b
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SRAM Slide 8 CMOS VLSI Design SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip N1 >> N2 bit bit_b N1 N2 P1 A P2 N3 N4 A_b word 0.0 0.5 1.0 1.5 0 100 200 300 400 500 600 time (ps) word bit A A_b bit_b
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This note was uploaded on 10/13/2009 for the course ECE 482 taught by Professor Adnanaziz during the Spring '07 term at University of Texas at Austin.

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lec13SRAM - Introduction to CMOS VLSI Design SRAM Outline...

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