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lec21Scaling - Introduction to CMOS VLSI Design Scaling and...

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Introduction to CMOS VLSI Design Scaling and Economics
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Scaling and Economics Slide 2 CMOS VLSI Design Outline Scaling Transistors Interconnect Future Challenges VLSI Economics
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Scaling and Economics Slide 3 CMOS VLSI Design Moore’s Law In 1965, Gordon Moore predicted the exponential growth of the number of transistors on an IC Transistor count doubled every year since invention Predicted > 65,000 transistors by 1975! Growth limited by power [Moore65]
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Scaling and Economics Slide 4 CMOS VLSI Design More Moore Transistor counts have doubled every 26 months for the past three decades. Year Transistors 4004 8008 8080 8086 80286 Intel386 Intel486 Pentium Pentium Pro Pentium II Pentium III Pentium 4 1,000 10,000 100,000 1,000,000 10,000,000 100,000,000 1,000,000,000 1970 1975 1980 1985 1990 1995 2000
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Scaling and Economics Slide 5 CMOS VLSI Design Speed Improvement Clock frequencies have also increased exponentially A corollary of Moore’s Law Year 1 10 100 1,000 10,000 1970 1975 1980 1985 1990 1995 2000 2005 4004 8008 8080 8086 80286 Intel386 Intel486 Pentium Pentium Pro/II/III Pentium 4 Clock Speed (MHz)
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Scaling and Economics Slide 6 CMOS VLSI Design Why? Why more transistors per IC? Why faster computers?
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Scaling and Economics Slide 7 CMOS VLSI Design Why? Why more transistors per IC? Smaller transistors Larger dice Why faster computers?
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Scaling and Economics Slide 8 CMOS VLSI Design Why? Why more transistors per IC? Smaller transistors Larger dice Why faster computers? Smaller, faster transistors Better microarchitecture (more IPC) Fewer gate delays per cycle
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Scaling and Economics Slide 9 CMOS VLSI Design Scaling The only constant in VLSI is constant change Feature size shrinks by 30% every 2-3 years Transistors become cheaper Transistors become faster Wires do not improve (and may get worse) Scale factor S Typically Technology nodes Year 0.1 1 10 1965 1970 1975 1980 1985 1990 1995 2000 2005 Feature Size ( μ m) 10 6 3 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 0.09 2 S =
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Scaling and Economics Slide 10 CMOS VLSI Design Scaling Assumptions What changes between technology nodes? Constant Field Scaling All dimensions (x, y, z => W, L, t ox ) Voltage (V DD ) Doping levels Lateral Scaling Only gate length L Often done as a quick gate shrink (S = 1.05)
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Scaling and Economics Slide 11 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 12 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 13 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 14 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 15 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 16 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 17 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 18 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 19 CMOS VLSI Design Device Scaling
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Scaling and Economics Slide 20 CMOS VLSI Design Device Scaling
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