lec14CamRomPla - Introduction to CMOS VLSI Design CAMs,...

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Introduction to CMOS VLSI Design CAMs, ROMs, and PLAs
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CAMS, ROMs and PLAs Slide 2 CMOS VLSI Design Outline Content-Addressable Memories Read-Only Memories Programmable Logic Arrays
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CAMS, ROMs and PLAs Slide 3 CMOS VLSI Design CAMs Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key CAM adr data/key match read write
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CAMS, ROMs and PLAs Slide 4 CMOS VLSI Design 10T CAM Cell Add four match transistors to 6T SRAM 56 x 43 λ unit cell bit bit_b word match cell cell_b
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CAMS, ROMs and PLAs Slide 5 CMOS VLSI Design CAM Cell Operation Read and write like ordinary SRAM For matching: Leave wordline low Precharge matchlines Place key on bitlines Matchlines evaluate Miss line Pseudo-nMOS NOR of match lines Goes high if no words match row decoder weak miss match0 match1 match2 match3 clk column circuitry CAM cell address data read/write
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CAMS, ROMs and PLAs Slide 6 CMOS VLSI Design Read-Only Memories Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed ROMs use one transistor per bit Presence or absence determines 1 or 0
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CAMS, ROMs and PLAs Slide 7 CMOS VLSI Design ROM Example 4-word x 6-bit ROM Represented with dot diagram Dots indicate 1’s in ROM Word 0: 010101 Word 1: 011001 Word 2: 100101 Word 3: 101010 ROM Array 2:4 DEC A0 A1 Y0 Y1 Y2 Y3 Y4 Y5 weak pseudo-nMOS pullups Looks like 6 4-input pseudo-nMOS NORs
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CAMS, ROMs and PLAs Slide 8 CMOS VLSI Design ROM Array Layout Unit cell is 12 x 8 λ (about 1/10 size of SRAM) Unit Cell
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This note was uploaded on 10/13/2009 for the course ECE 482 taught by Professor Adnanaziz during the Spring '07 term at University of Texas.

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lec14CamRomPla - Introduction to CMOS VLSI Design CAMs,...

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