lec19DesignForSkew - Introduction to CMOS VLSI Design...

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Unformatted text preview: Introduction to CMOS VLSI Design Design for Skew Design for Skew Slide 2 CMOS VLSI Design Outline Clock Distribution Clock Skew Skew-Tolerant Static Circuits Traditional Domino Circuits Skew-Tolerant Domino Circuits Design for Skew Slide 3 CMOS VLSI Design Clocking Synchronous systems use a clock to keep operations in sequence – Distinguish this from previous or next – Determine speed at which machine operates Clock must be distributed to all the sequencing elements – Flip-flops and latches Also distribute clock to other elements – Domino circuits and memories Design for Skew Slide 4 CMOS VLSI Design Clock Distribution On a small chip, the clock distribution network is just a wire – And possibly an inverter for clkb On practical chips, the RC delay of the wire resistance and gate load is very long – Variations in this delay cause clock to get to different elements at different times – This is called clock skew Most chips use repeaters to buffer the clock and equalize the delay – Reduces but doesn’t eliminate skew Design for Skew Slide 5 CMOS VLSI Design Example Skew comes from differences in gate and wire delay – With right buffer sizing, clk 1 and clk 2 could ideally arrive at the same time. – But power supply noise changes buffer delays – clk 2 and clk 3 will always see RC skew 3 mm 1.3 pF 3.1 mm gclk clk 1 0.5 mm clk 2 clk 3 0.4 pF 0.4 pF Design for Skew Slide 6 CMOS VLSI Design Review: Skew Impact F1 F2 clk clk clk Combinational Logic T c Q1 D2 Q1 D2 t skew CL Q1 D2 F1 clk Q1 F2 clk D2 clk t skew t setup t pcq t pdq t cd t hold t ccq ( 29 setup skew sequencing overhead hold skew pd c pcq cd ccq t T t t t t t t t ≤- + + ≥- + 1 4 442 4 4 43 Ideally full cycle is available for work Skew adds sequencing overhead Increases hold time too Design for Skew Slide 7 CMOS VLSI Design Cycle Time Trends Much of CPU performance comes from higher f – f is improving faster than simple process shrinks – Sequencing overhead is bigger part of cycle 0.01 0.1 1 10 100 80386 80486 Pentium Pentium II / III SpecInt95 1985 1988 1991 1994 1997 2000 1.2 0.8 0.6 0.35 2.0 Process 100 200 500 V DD = 5 V DD = 3.3 V DD = 2.5 50 Fanout-of-4 (FO4) Inverter Delay (ps)...
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This note was uploaded on 10/13/2009 for the course ECE 482 taught by Professor Adnanaziz during the Spring '07 term at University of Texas at Austin.

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lec19DesignForSkew - Introduction to CMOS VLSI Design...

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