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lec19DesignForSkew - Introduction to CMOS VLSI Design...

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Introduction to CMOS VLSI Design Design for Skew
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Design for Skew Slide 2 CMOS VLSI Design Outline Clock Distribution Clock Skew Skew-Tolerant Static Circuits Traditional Domino Circuits Skew-Tolerant Domino Circuits
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Design for Skew Slide 3 CMOS VLSI Design Clocking Synchronous systems use a clock to keep operations in sequence Distinguish this from previous or next Determine speed at which machine operates Clock must be distributed to all the sequencing elements Flip-flops and latches Also distribute clock to other elements Domino circuits and memories
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Design for Skew Slide 4 CMOS VLSI Design Clock Distribution On a small chip, the clock distribution network is just a wire And possibly an inverter for clkb On practical chips, the RC delay of the wire resistance and gate load is very long Variations in this delay cause clock to get to different elements at different times This is called clock skew Most chips use repeaters to buffer the clock and equalize the delay Reduces but doesn’t eliminate skew
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Design for Skew Slide 5 CMOS VLSI Design Example Skew comes from differences in gate and wire delay With right buffer sizing, clk 1 and clk 2 could ideally arrive at the same time. But power supply noise changes buffer delays – clk 2 and clk 3 will always see RC skew 3 mm 1.3 pF 3.1 mm gclk clk 1 0.5 mm clk 2 clk 3 0.4 pF 0.4 pF
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Design for Skew Slide 6 CMOS VLSI Design Review: Skew Impact F1 F2 clk clk clk Combinational Logic T c Q1 D2 Q1 D2 t skew CL Q1 D2 F1 clk Q1 F2 clk D2 clk t skew t setup t pcq t pdq t cd t hold t ccq ( 29 setup skew sequencing overhead hold skew pd c pcq cd ccq t T t t t t t t t - + + - + 1 4 442 4 4 43 Ideally full cycle is available for work Skew adds sequencing overhead Increases hold time too
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Design for Skew Slide 7 CMOS VLSI Design Cycle Time Trends Much of CPU performance comes from higher f f is improving faster than simple process shrinks Sequencing overhead is bigger part of cycle 0 . 0 1 0 . 1 1 1 0 1 0 0 8 0 3 8 6 8 0 4 8 6 P e n t i u m P e n t i u m I I / I I I S p e c I n t 9 5 1 9 8 5 1 9 8 8 1 9 9 1 1 9 9 4 1 9 9 7 2 0 0 0 1 . 2 0 . 8 0 . 6 0 . 3 5 2 . 0 P r o c e s s 1 0 0 2 0 0 5 0 0 V D D = 5 V D D = 3 . 3 V D D = 2 . 5 5 0 F a n o u t - o f - 4 ( F O 4 ) I n v e r t e r D e l a y ( p s ) 0 . 2 5 1 0 1 0 0 1 0 0 0 8 0 3 8 6 8 0 4 8 6 P e n t i u m P e n t i u m I I / I I I M H z 1 9 8 8
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