lec23Conclusion - CMOS VLSI Design Digital Design Digital...

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Digital Design Slide 1 CMOS VLSI CMOS VLSI Design Digital Design
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Digital Design Slide 2 CMOS VLSI Overview Physical principles Combinational logic Sequential logic Datapath Memories Trends
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Digital Design Slide 3 CMOS VLSI Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type) As Si Si Si Si Si Si Si Si B Si Si Si Si Si Si Si Si - + + -
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Digital Design Slide 4 CMOS VLSI nMOS Operation Body is commonly tied to ground (0 V) When the gate is at a low voltage: P-type body is at low voltage Source-body and drain-body diodes are OFF No current flows, transistor is OFF n+ p Gate Source Drain bulk Si SiO 2 Polysilicon n+ D 0 S
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Digital Design Slide 5 CMOS VLSI Transistors as Switches We can view MOS transistors as electrically controlled switches Voltage at gate controls path from source to drain g s d g = 0 s d g = 1 s d g s d s d s d nMOS pMOS OFF ON ON OFF
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Digital Design Slide 6 CMOS VLSI CMOS Inverter A Y 0 1 V DD A Y GND A Y
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Digital Design Slide 7 CMOS VLSI Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors n+ p substrate p+ n well A Y GND V DD n+ p+ SiO 2 n+ diffusion p+ diffusion polysilicon metal1 nMOS transistor pMOS transistor
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Digital Design Slide 8 CMOS VLSI Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line GND V DD Y A substrate tap well tap nMOS transistor pMOS transistor
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Digital Design Slide 9 CMOS VLSI Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well – Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer – Strip off SiO 2 p substrate
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Digital Design Slide 10 CMOS VLSI Oxidation Grow SiO 2 on top of Si wafer – 900 – 1200 C with H 2 O or O 2 in oxidation furnace p substrate SiO 2
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Digital Design Slide 11 CMOS VLSI Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light p substrate SiO 2 Photoresist
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Digital Design Slide 12 CMOS VLSI Lithography Expose photoresist through n-well mask Strip off exposed photoresist p substrate SiO 2 Photoresist
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Digital Design Slide 13 CMOS VLSI Etch Etch oxide with hydrofluoric acid (HF) Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed p substrate SiO 2 Photoresist
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Digital Design Slide 14 CMOS VLSI Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step p substrate SiO 2
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Digital Design Slide 15 CMOS VLSI n-well n-well is formed with diffusion or ion implantation Diffusion
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This note was uploaded on 10/13/2009 for the course ECE 482 taught by Professor Adnanaziz during the Spring '07 term at University of Texas at Austin.

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lec23Conclusion - CMOS VLSI Design Digital Design Digital...

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