On the Construction of ZeroDeficiency
Parallel Prefix Circuits with Minimum Depth
HAIKUN ZHU, CHUNGKUAN CHENG, and RONALD GRAHAM
University of California, San Diego
A parallel prefix circuit has
n
inputs
x
1
,
x
2
,
...
,
x
n
, and computes the
n
outputs
y
i
=
x
i
•
x
i
−
1
•···•
x
1
, 1
≤
i
≤
n
, in parallel, where
•
is an arbitrary binary associative operator. Snir proved that the
depth
t
and size
s
of any parallel prefix circuit satisfy the inequality
t
+
s
≥
2
n
−
2. Hence, a parallel
prefix circuit is said to be of zerodeficiency if equality holds. In this article, we provide a different
proof for Snir’s theorem by capturing the structural information of zerodeficiency prefix circuits.
Following our proof, we propose a new kind of zerodeficiency prefix circuit
Z
(
d
) by constructing
a prefix circuit as wide as possible for a given depth
d
. It is proved that the
Z
(
d
) circuit has the
minimal depth among all possible zerodeficiency prefix circuits.
Categories and Subject Descriptors: B.6.1 [
Logic Design
]: Design Styles—
Parallel circuits
General Terms: Algorithms, Design, Theory
Additional Key Words and Phrases: Zerodeficiency, parallel prefix circuits, depthsize tradeoff
1. INTRODUCTION
1.1 Problem Definition
The prefix problem, which mostly gains research attention with the emergence
of parallel computing, is actually the abstraction of many practical applications
such as binary addition, radix sort, linear recurrences solving, polynomial eval
uation, etc. [Lakshmivarahan and Dhall 1994]. Formally, the prefix problem is
defined as follows:
Definition
1.1
.
[Prefix Problem]
Given
n
inputs
x
1
,
x
2
,
...
,
x
n
and an ar
bitrary binary associative operator
•
, compute the prefix results
Y
i
=
x
i
•
x
i
−
1
•
··· •
x
1
for 1
≤
i
≤
n
.
This article is based on work previously published as “Constructing ZeroDeficiency Parallel Prefix
Adder of Minimum Depth,” In
Proceedings of the 2005 Asia and South Pacific Design Automation
Conference
(
ASPDAC 2005
)
.
c 2005 IEEE.
This work was supported in part under grants from National Science Foundation (NSF) project
number MIP9987678, the California MICRO program, and SRC support.
Authors’ address: Computer Science and Engineering, University of California, San Diego, La Jolla,
CA 920930404; email:
{
hazhu,kuan,rgraham
}
@cs.ucsd.edu
.
Permission to make digital or hard copies of part or all of this work for personal or classroom use is
granted without fee provided that copies are not made or distributed for profit or direct commercial
advantage and that copies show this notice on the first page or initial screen of a display along
with the full citation. Copyrights for components of this work owned by others than ACM must be
honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers,
to redistribute to lists, or to use any component of this work in other works requires prior specific
permission and/or a fee. Permissions may be requested from Publications Dept., ACM, Inc., 1515
Broadway, New York, NY 10036 USA, fax:
+
1 (212) 8690481, or [email protected]
This preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
This is the end of the preview.
Sign up
to
access the rest of the document.
 Spring '07
 AdnanAziz
 electronic systems, Parallel algorithm, prefix circuit, prefix circuits

Click to edit the document details