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eecs355_W08_hw02

eecs355_W08_hw02 - cycle L2 is lit Draw a state diagram of...

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EECS 355 ASIC & FPGA Design Assignment 2 Due January 25 Note: Work on the assignments alone and create your individual original answers. For all problems provide the code including the testbench and the simulation waveforms of relevant signals. Problem 1. Exercise 3.3 (HDL Programming Fundamentals, Botros) Problem 2. Design a circuit capable of counting the number of clock events (number of rising edges + falling edges). Write a test bench for the model, and test it using a VHDL simulator. Problem 3 . FSM Design: Here you will design a Moore finite state machine that controls three LEDs. A simple block diagram of the design is shown in the figure below. The LEDs will be lit in different sequences depending on the Control input. Only one or zero LEDs are lit at the same time. When Reset is active, all LEDs will be off. The table below shows a functional description of the FSM.

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For instance L1 Æ L2 means that in the first clock cycle L1 is lit and in the next clock
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Unformatted text preview: cycle L2 is lit. Draw a state diagram of your Moore FSM and write a VHDL model of the FSM using the entity declaration below. Write a test bench for the model, and test it using a VHDL simulator. library ieee; use ieee.std_logic_1164.all; entity FSM is port ( Clk : in std_logic; -- Clock Reset : in std_logic; -- Active high asynch reset Control : in std_logic_vector(1 downto 0); L1, L2, L3 : out std_logic -- LED Outputs ); end FSM; Problem 4. Comparator: Construct a circuit capable of comparing two 8-bit vectors, a, and b. A selection bit (sel) should determine wether the comparison is signed (sel=’1’) or unsigned (sel=’0’). The circuit must have three outputs, x1, x2, and x3, corresponding to a>b, a=b, and a<b, respectively. Design a circuit in VHDL using only sequential (behavioral) code. Write a test bench for the model, and test it using a VHDL simulator....
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eecs355_W08_hw02 - cycle L2 is lit Draw a state diagram of...

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