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Unformatted text preview: cycle L2 is lit. Draw a state diagram of your Moore FSM and write a VHDL model of the FSM using the entity declaration below. Write a test bench for the model, and test it using a VHDL simulator. library ieee; use ieee.std_logic_1164.all; entity FSM is port ( Clk : in std_logic; -- Clock Reset : in std_logic; -- Active high asynch reset Control : in std_logic_vector(1 downto 0); L1, L2, L3 : out std_logic -- LED Outputs ); end FSM; Problem 4. Comparator: Construct a circuit capable of comparing two 8-bit vectors, a, and b. A selection bit (sel) should determine wether the comparison is signed (sel=1) or unsigned (sel=0). The circuit must have three outputs, x1, x2, and x3, corresponding to a>b, a=b, and a<b, respectively. Design a circuit in VHDL using only sequential (behavioral) code. Write a test bench for the model, and test it using a VHDL simulator....
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This note was uploaded on 10/14/2009 for the course EECS 241 taught by Professor Gou during the Winter '09 term at Northwestern.
- Winter '09