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Unformatted text preview: Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4G Wireless Standards * Yang Sun , Yuming Zhu , Manish Goel , and Joseph R. Cavallaro ECE Department, Rice University. 6100 Main, Houston, TX 77005 DSPS R&D Center, Texas Instruments. 12500 TI Blvd MS 8649, Dallas, TX 75243 Email: email@example.com, firstname.lastname@example.org, email@example.com, firstname.lastname@example.org Abstract In this paper, we propose a novel multi-code turbo de- coder architecture for 4G wireless systems. To support var- ious 4G standards, a configurable multi-mode MAP (max- imum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tai- lored to the given throughput requirements. High-level parallelism is achieved by employing contention-free inter- leavers. Multi-banked memory structure and routing net- work among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate. 1. Introduction The approaching fourth-generation (4G) wireless sys- tems are projected to provide 100 Mbps to 1 Gbps speeds by 2010, which consequently leads to orders of magnitude increases in the expenditure of the computing resources. The high throughput turbo codes  are required in many 4G communication applications. 3GPP Long Term Evo- lution (LTE) and IEEE 802.16e WiMax are two examples. As some 4G systems use different types of turbo coding schemes (e.g. binary codes in 3GPP LTE and duo-binary codes in WiMax), a general solution to supporting multiple code types is to use programmable processors. For exam- * This work was supported by the Summer Student Program 2007, Texas Instrument Incorporated. ple, a 2 Mbps turbo decoder implemented on a DSP proces- sor is proposed in . Also, authors in  and  develop a multi-code turbo decoder based on SIMD processors, where a 5.48 Mbps data rate is achieved in  and a 100 Mbps data rate is achieved in  at a cost of 16 processors. While these programmable SIMD/VLIW processors offer great flexibil- ities, they have several disadvantages notably higher power consumption and less throughput than ASIC solutions. A turbo decoder is typically one of the most computation- intensive parts in a 4G receiver, therefore it is essential to design an area and power efficient turbo decoder in ASIC....
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This note was uploaded on 10/15/2009 for the course COMMUNICAR IEE 126 taught by Professor M.j.liu during the Spring '09 term at The School of the Art Institute of Chicago.
- Spring '09