Lecture 13 - Th The University of Texas at Dallas Erik...

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Erik Jonsson School of Engineering and h U i it f T t D ll Computer Science The University of Texas at Dallas MIPS Memory Instructions The MIPS load-store architecture limits memory access. Data transfers occur only via load/store operations. Register indirect addressing – register contains memory address of operand; used in load/store instructions (“i-format” instructions). Displacement-based or indexed addressing – register plus numerical offset in instruction are added for memory address; used in load/store instructions his is a variation of register indirect addressing also “i rmat”) (this is a variation of register indirect addressing, also i-format ). Instruction memory (via the program counter) is accessed only by jump or branch instructions. Direct addressing – instruction contains an absolute memory address; used in jump instructions (“j-format” instructions). Register indirect addressing – register contains memory address of operand; used in jr instructions (“i-format” instruction). Relative addressing – numerical offset in instruction added algebraically to © N. B. Dodge 09/09 Lecture #13: Memory Reference Instructions 1 program counter to obtain operand address; used in branch instructions (discussed in a later lecture – also an “i-format” instruction).
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Erik Jonsson School of Engineering and h U i it f T t D ll Computer Science The University of Texas at Dallas Load Instruction Format Op Code $rs (Add) $rt (Dest.) Offset to be added to source reg. Defines operation Base address Offset added to base address (±32,768) 6 bits 5 bits 5 bits 16 bits (15 bits magnitude + sign bit) Load instructions use the i-format. data destination Load instructions transfer a 32-bit word, a 16-bit halfword, or an 8- bit byte into a designated register from memory. The “Op Code” defines the load instruction. Examples: 0x 23 (10 0011) = load word, load halfword is 0x21, and load byte is 0x20. $rs is the 5-bit address of a source register . The location of the data is calculated as [$rs] + Imm. = data address. ([ ] = “contents of”) © N. B. Dodge 09/09 Lecture #13: Memory Reference Instructions 2 The data is loaded from memory into $rt, the destination register.
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Erik Jonsson School of Engineering and h U i it f T t D ll Computer Science The University of Texas at Dallas Load Byte Instruction 1010 000 0000 0011 0000 Op Code = “lb” Base address is in $t2 (=$10) Offset = + 0x 30 (= + 48) 10 0000 0 1010 0 1111 0000 0000 0011 0000 Destination register is $t7 (=$15) Load byte (lb) is the simplest of the load instructions. An example is shown above: “Load the byte at the address comprised of [$t2] + 0x30 into destination register $t7.” thi l th i l b t t th dd $t2] + 48) In this case, only the single byte at the address ([$t2] + 48) is loaded into the lowest 8 bits of $t7. The other 24 bits of $t7 match the sign bit of the byte – this is called “sign extension.” ote: emory is byte- ddressable Tha ti s , ery single byte in © N. B. Dodge 09/09 Lecture #13: Memory Reference Instructions 3 Note: Memory is byte addressable . That is, every single byte in MIPS memory has a unique, individual address .
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This note was uploaded on 10/16/2009 for the course EE 2310 taught by Professor Dodge during the Spring '09 term at University of Texas at Dallas, Richardson.

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Lecture 13 - Th The University of Texas at Dallas Erik...

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