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# Lecture 9 - Th The University of Texas at Dallas Erik...

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Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas Take-Home Exercise Assume you want the counter below to count mod-8 backward . That is, it would count 0-7-6-5-4-3-2-1-0, etc. Assume it is reset on start-up, and design the wiring to make the counter count properly. Major hint that was supplied: Remember the K-map method will work for ANY counter. Note: x is the most significant bit, z the least significant. z y x © N. B. Dodge 09/09 Lecture #9: Designing Digital Sequential Logic Circuits 1

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Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas Exercise 1 Clock Reset y x C id th 2 T FF’ b Wh t if t d t i th i t Consider the 2 T FF’s above. What if we wanted to wire them into a modulo-3 backwards counter, i.e., one that counts 2-1-0, 2-1-0? This can be done rather easily if you use the K-map method and consider how each stage behaves separately on each count © N. B. Dodge 09/09 Lecture #9: Designing Digital Sequential Logic Circuits 5 consider how each stage behaves separately on each count.
Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas Designing Sequential Logic Last lecture demonstrated the design of two simple counters (a third counter was a simple counters (a third counter was a homework problem). Today’s exercise: Three additional designs: Today s exercise: Three additional designs: A timer or signal generator A “sequential” multiplexer A modulo-10 binary counter Note that all the designs utilize counters. © N. B. Dodge 09/09 Lecture #9: Designing Digital Sequential Logic Circuits 8

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Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas A Signal Generator The desired design is a signal generator based on a counter. Specification: 4 bit bi h ( ll l) t d i b 50/50 l k 4-bit binary synchronous (parallel) counter, driven by a 50/50 clock. Counter runs continually, reset only at startup by a “Reset-” signal. Since 2 4 = 16, counter counts modulo-16. C t t i l ” t 3 7 d 14 hi h Counter generates “sync signals” on counts 3, 7, and 14, which: Occur immediately after the counts are valid (i.e., immediately after the counter output stages change). Occur for 1/2 clock cycle only . Per “spec,” we need a 4-bit counter. We can use the standard T FF that we used to build the 3-bit counter in the last lesson. We ill d f f th © N. B. Dodge 09/09 Lecture #9: Designing Digital Sequential Logic Circuits 9 will need four of these.
Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas Designing the Timer Clock inputs are connected to the counter as shown above (all counter inputs driven by system clock, since counter is parallel ).

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• Spring '09
• Dodge
• sequential logic circuits, Erik Jonsson School, N. B. Dodge, Erik Jonsson School of Engineering and Computer Science, Designing Digital Sequential

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Lecture 9 - Th The University of Texas at Dallas Erik...

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