# Lecture 8 - Th The University of Texas at Dallas Erik...

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Erik Jonsson School of Engineering and h U i it f T t D ll Computer Science The University of Texas at Dallas The Storage or Data Register All sequential logic circuits in the computer CPU are based on the latch or flip-flop. A significant part of the ALU is the register complement . In the MIPS R-2000 computer which we will study shortly, there are thirty-two 32-bit registers, generally called “storage registers .” A storage register is a set of D FF’s (generally master-slave D FF’s) which work in unison to store the number of bits in a computer data word. In the case of the R-2000, each register has 32 D FF’s to store 32 bits of data simultaneously. To more fully understand the concept of the data storage register, we first need to discuss and understand the data bus . © N. B. Dodge 09/09 Lecture #8: Registers, Counters, and Other Latch-Based Circuits 1

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Erik Jonsson School of Engineering and h U i it f T t D ll Computer Science The University of Texas at Dallas The Data Bus A data bus is a collection of wires (or copper lines on a rinted circuit board or metal conductors on a printed circuit board or metal conductors on a semiconductor chip) which carry data (bits) in parallel from one part of a computer to another. The MIPS R-2000 has 32-bit data words , so that 32 data bits are transferred in parallel in data transfers. That i , the MIPS R-2000 has 32- it data buses s, eS 000 s 3 b d buses . There are various buses in the CPU of most computers, but those that carry data are called “data buses.” © N. B. Dodge 09/09 Lecture #8: Registers, Counters, and Other Latch-Based Circuits 2 Data on the buses are 1’s and 0’s (two voltage levels).
Erik Jonsson School of Engineering and h U i it f T t D ll Computer Science The University of Texas at Dallas Data Bus Illustration Clock 8-bit Storage Register CLK D7 Q7 Q7 Q6 D7 D6 LK Input Data Output Data D6 D5 D4 D3 D2 D1 D0 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Etc. Etc. CLK The storage register shown above is connected to two 8-bit buses. Bus (8 Lines) Bus (8 Lines) The 8 data lines are connected to the 8 inputs of the storage register. Similarly, register outputs are connected to the 8 output bus lines. Data is input to the register in parallel . That is, 8 bits (0 or 1) are © N. B. Dodge 09/09 Lecture #8: Registers, Counters, and Other Latch-Based Circuits 3 placed on the lines and stored in the register on one clock pulse.

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Erik Jonsson School of Engineering and h U i it f T t D ll Computer Science The University of Texas at Dallas The Concept of Data “Gating” The data bus is a conduit which links registers to the ALU. Generally, an ALU has two input buses, to which all register outputs are electrically. A second bus from the ALU returns results of ALU operation to all the register inputs .
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• Spring '09
• Dodge
• Central processing unit, Flip-flop, Erik Jonsson School, N. B. Dodge, Erik Jonsson School of Engineering and Computer Science

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Lecture 8 - Th The University of Texas at Dallas Erik...

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