{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

# Lecture 6 - Th The University of Texas at Dallas Erik...

This preview shows pages 1–5. Sign up to view the full content.

Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas Sequential Logic and Clocked Circuits Up to now in our study of digital circuits, we have studied combinational logic . A combinational logic circuit operates such that the output of the circuit depends only on the input(s) . We now move on to sequential logic , which makes up a large portion of the digital circuits in computers. Sequential logic differs from combinational logic in several ways: Its outputs depend not only on logic inputs but also the internal state of the logic . The output of sequential logic does not necessarily change when an input changes, but is synchronized to some “triggering event.” Sequential logic is often synchronized or triggered by a train of © N. B. Dodge 09/09 Lecture #6: Fundamentals of Sequential Logic Circuits 1 regular pulses on a serial input line, which is referred to as a “clock.”

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas Representation of Sequential Logic State or M Combinational L i Clock or Timing Memory Element Logic Elements Device Output Input Sequential logic has inputs and outputs like combinational logic. It also has a timing (synchronizing) mechanism and state or memory element(s) Variables a timing (synchronizing) mechanism and state or memory element(s). Sequential logic may (usually will) have combinational parts. Sequential logic outputs depend on the timing and state elements as well as the input variables. That is, the outputs normally change as a function of © N. B. Dodge 09/09 Lecture #6: Fundamentals of Sequential Logic Circuits 2 the timing element .
Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas The Simple Latch or R-S Flip-Flop Q Set R-S Flip-Flop Q Reset The simplest example of a sequential logic device is the R-S latch or R-S flip-flop (R-S FF). This is a non-clocked device that simply consists of two cross- connected 2-input NAND gates ( it may also be represented as combinations of other gates ). Note that per our definition, the R-S FF has an output that © N. B. Dodge 09/09 Lecture #6: Fundamentals of Sequential Logic Circuits 3 depends on its current state as well as the inputs.

This preview has intentionally blurred sections. Sign up to view the full version.

View Full Document
Erik Jonsson School of Engineering and Th U i it f T t D ll Computer Science The University of Texas at Dallas The Simple Latch or R-S Flip-Flop (2) Q Set R-S Flip-Flop Q Reset This most basic form of the R-S FF uses “negative-true” input logic. That is, it changes states based on inputs that transition to 0 , not to 1. When the Q output is 1 and Q=0, the R-S FF is said to be “set.” Likewise, when Q=0 and Q=1, the flip-flop is said to be “reset.” Q and Q will always have opposite states.
This is the end of the preview. Sign up to access the rest of the document.

{[ snackBarMessage ]}

### Page1 / 27

Lecture 6 - Th The University of Texas at Dallas Erik...

This preview shows document pages 1 - 5. Sign up to view the full document.

View Full Document
Ask a homework question - tutors are online