# 9-comb - 9/10/09 Combinational Logic •  A combinational...

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Unformatted text preview: 9/10/09 Combinational Logic •  A combinational logic circuit has: ECE2030 Introduction to Computer Engineering Lecture 8: Combinational and Mixed Logic 1 2 •  A set of N Boolean inputs and M Boolean outputs •  M switching functions, each mapping the 2N input combinations to an output such that outputs, “at any time”, are determined by the input combination •  When input changed, output changed immediately •  Note that real circuits are imperfect and have “propagation delay” •  A combinational circuit •  Performs logic operations that can be specified by a set of Boolean expressions •  Can be built hierarchically N inputs Combinational circuits M outputs Design Hierarchy Example X0 X1 X2 X3 X4 X5 X6 X7 X8 Derive Truth Table for Desired Functionality A 0 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 F 0 1 1 0 1 0 0 1 A BC 00 0 1 0 1 01 1 0 11 0 1 10 1 0 9-input Odd Function 9-input Odd Function Z X0 X1 X2 X3 X4 X5 X6 X7 X8 A0 A1 A2 A0 A1 A2 A0 A1 A2 3-input B0 Odd Function 3-input B0 Odd Function 3-input B0 Odd Function A0 A1 A2 0 3-input Odd Function 0 Function Specification: To detect odd number of “1” inputs, i.e. Z=1 when there is an odd number of “1” present in the inputs Z 0 1 1 1 1 How to design a 3-input Odd Function? Function Specification: To detect odd number of “1” inputs, i.e. Z=1 when there is an odd number of “1” present in the inputs 3 4 1 9/10/09 Design Hierarchy Example 1.  X0 X1 X2 X3 X4 X5 X6 X7 X8 Design Procedure Specification •  Write a specification for the circuit if one not available 9-input Odd Function 9-input Odd Function Z 2.  X0 X1 X2 X3 X4 X5 X6 X7 X8 A0 A1 A2 A0 A1 A2 A0 A1 A2 Formulation •  •  Derive a truth table or initial Boolean equations that define the required relationships between the inputs and outputs Apply hierarchical design if appropriate 3-input B0 Odd Function 3-input B0 Odd Function 3-input B0 Odd Function A0 A1 A2 3-input Odd Function Z 3.  •  •  Optimization Apply 2-level and multiple-level optimization Draw a logic diagram or provide a netlist for the resulting circuit using ANDs, ORs, and inverters 3-input Odd function: B0=A0 ⊕A1⊕A2 4. •  Technology Mapping Map the logic diagram to the implementation technology selected A0 A1 A2 5 6 B0 5. •  Verification Verify the correctness of the final design manually or using simulation Design Example 1.  Specification •  Design a code converter – a circuit which translates information from one binary code to another. •  Example: BCD-to-Excess-3 Code Converter •  •  Binary combination of binary coded decimal digits 0-9 (represented by binary) plus 3 Example •  •  Input = 5 Output = 5 + 3 = 8 (or 1000 in binary) Design Example (continued) 2.  Formulation •  •  Conversion of 4-bit codes can be most easily formulated by a truth table Variables - BCD: A,B,C,D Variables - Excess-3 W,X,Y,Z Don’t Cares •  •  8 •  •  •  Implementation: •  multiple-level circuit •  NAND gates (including inverters) 7 Digits > 9 BCD 1010 to 1111 2 9/10/09 Design Example (continued) 3.  Optimization a.  2-level using K-maps A W = A + BC + BD X = B C + B D +B C D Y = CD + C D x Z=D z Design Example (continued) C C 1 0 1 3 y 1 2 1 0 1 1 3 2 3.  Optimization (continued) 6 1 4 5 7 1 6 1 1 4 5 7 b.  Multiple-level using transformations B W = A + BC + BD X = B C + B D +B C D Y = CD + C D Z= D Gate Input Cost = 26 X 12 X 13 8 9 X 15 X 14 B A X 12 X 13 8 9 X 15 X 14 1 X 11 X 10 1 X 11 X 10 D C 1 0 1 D w 2 0 1 C 3 2 •  When using a shared subexpression: T1 = C + D W = A + BT1 X = B T1 + BC D Y = CD + C D Z= D 1 3 7 1 1 1 7 1 4 5 6 1 6 X X 13 X 15 X 14 B A 4 5 X 12 X 13 X 15 X 14 B A 9 12 1 8 9 X 11 X 10 1 8 1 9 X 11 X 10 Gate Input Cost= 19 D D 10 Design Example (continued) 4.  Technology Mapping - Create the Logic diagram for the circuit by mapping •  To NAND Gates A •  To NOR Gates W Technology Mapping •  Mapping to NAND or NOR gates is accomplished by: •  Replacing AND and OR symbols, •  Canceling inverter pairs A A B B C F A (a) B C Z E B X C D E C D Y D E F (c) 1 X 3 2 F (b) D 12 11 3 9/10/09 Verification •  Verification - show that the final circuit designed implements the original specification •  Simple specifications are: •  truth tables •  Boolean equations Verification Example •  BCD-to-Excess 3 Code Converter •  Find the SOP Boolean equations from the final circuit. •  Find the truth table from these equations •  Compare to the formulation truth table •  Finding the Boolean Equations: T1 = C + D = C + D W = A (T1 B) = A + B T1 X = (T1 B) (B C D) = B T1 + BC D Y = C D + C D = CD + CD 13 14 Verification Example •  Find the circuit truth table from the equations and compare to specification truth table: Mixed Logic •  Let’s revisit Technology Mapping •  The reason for technology mapping … it enables component reuse •  Mixed Logic allows a digital logic circuit designer to implement a combinational logic with •  Only NAND gates •  Only NOR gates •  Only NAND and NOR gates 16 Input BCD ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 15 Output Excess -3 WXYZ 0011 0100 0101 0110 0111 1000 1001 1010 1011 1011 The tables match! 4 9/10/09 DeMorgan’s Law B C A D Example: Mixed Logic (1) •  Implement all ORs •  Implement all ANDs •  Forget all the inversion at this moment 17 18 Example: Mixed Logic (2) B C A D A B C Example: Mixed Logic (3) •  Draw “Vertical Bars” in the circuits where all complements in the Boolean equation occur •  Draw a bubble on each Vertical Bar D •  Convert each gate to the desired gate by inserting a bubble in front of the gate •  Use DeMorgan’s Law •  OR ⇒ NAND: by adding 2 bubbles on the inputs side of OR •  AND ⇒ NOR: by adding 2 bubbles on the inputs side of the AND 19 20 5 9/10/09 Example: Mixed Logic (4) How about Inverters? •  Inverters can be implemented by either a NAND or a NOR gate •  Wiring the inputs together B C A D •  Replace “vertical bars with bubbles” with inverters 21 22 Example: Mixed Logic (Final) Example: Mixed Logic (Final) B C A D B C A D 23 24 6 9/10/09 Mixed Logic •  How about build the prior circuits with only NOR gates? Example: Mixed Logic (1) B C A D 25 26 Example: Mixed Logic (2) Example: Mixed Logic (3) B C A D B C A D 27 28 7 9/10/09 Example: Mixed Logic (4) Example: Mixed Logic (4) B C A D B C A D 29 30 Example: Mixed Logic (Final) Mixed Logic Example II (1) C B C A D D B A 31 32 8 9/10/09 Mixed Logic Example II (2) Mixed Logic Example II (3) C D B A C D B A 33 34 Mixed Logic Example II (4) Mixed Logic Example II (5) C D B A C D B A 35 36 9 9/10/09 Mixed Logic Example II (6) Mixed Logic Example II (7) C D B A C D B A 37 38 Mixed Logic Example III (1) B D A C B D A C Mixed Logic Example III (2) 39 40 10 9/10/09 Mixed Logic Example III (3) B D A C B D A C Mixed Logic Example III (4) 41 42 Mixed Logic Example III (5) B D A C B D A C Mixed Logic Example III (6) 43 44 11 9/10/09 Mixed Logic Example III (7) B D A C 45 12 ...
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## This note was uploaded on 10/20/2009 for the course COE 1 taught by Professor Many during the Spring '09 term at Georgia Institute of Technology.

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