Unformatted text preview: ingly SIR and SOR at the rightmost bit (lsb). (Hint: you need a 2-bit control signal) 5. Construct a timing diagram for the shift register designed above. Set the control signals to parallel load the value ‘101’ in cycle 1, and then shift left for three subsequent cycles. Input SIR should be set to ‘0’ for all cycles. Show the values for all three bits of the shift register, and the value of SOL for all four cycles. Spring 2009 Due: 24.2.2009 Prof. David Schimmel Section F...
View Full Document
This note was uploaded on 10/20/2009 for the course COE 1 taught by Professor Many during the Spring '09 term at Georgia Tech.
- Spring '09