作业_60

作业_60 -...

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Unformatted text preview: 200628017029197 1 > e (p → q) ◇ & > e p 0 q0 12 1 : ≤ ≤ x p 12 : = x q 1 2 3 4 5 6… x 6 12 18 24 30 36… Q F F T F F F F… q ◇ T T T F F F F… p F T T F F F F… p → q ◇ T T T T T T T… (p → q) ◇ T T T T T T T… 2 SMV 0 The alternating bit protocol. (sender 0 receiver = LTLSPEC st=sent. ◇ LTLSPEC st=received. ◇ AB 0 U sA [[[ [ [ > [= = { sA 1 [ > [= = { sA 1 [ > [= = R sA 1 sA MODULE sender(ch_s2r, ch_r2s, sa) VAR state : {s0, s1, s2, s3, s4, s5} ASSIGN init(state) := s0; next(state) := case state = s0 & sa = sendd0 : s1;--if the user wants to send data0 s0->s1; state = s1 & (ch_s2r = empty) : s2;--if the channel from sender to receiver is empty s1->s2; state = s2 & (ch_r2s = ack0) : {s1, s3};--if timeout s2->s1; else if sender receives ack0 s2->s3; state = s2 & (ch_r2s = ack1) : {s1};--if sender receives ack1 s2->s1; state = s3 & sa = sendd1 : s4;--if the user wants to send data1 s3->s4; state = s4 & (ch_s2r = empty) : s5;--if the channel from sender to receiver is empty s4->s5;...
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