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Unformatted text preview: subparagraphs (c)(1) and (2) of Commercial Computer Software -- Restricted Rights at 48 CFR 52.227-19, as applicable. Cadence Design Systems, Inc. 555 River Oaks Parkway San Jose, California 95134 For technical assistance please contact the Cadence Response Center at 1-877-CDS-4911 or send email to email@example.com For more information on Cadence's Verilog-XL product line send email to firstname.lastname@example.org Compiling source file "test.v" Compiling source file "circuit1.v" Compiling source file "prebuilt_gates.v" Highest level modules: test_fixture AND2 NOR2 INV L67 "test.v": $finish at simulation time 400 0 simulation events (use +profile or +listcounts option to count) CPU time: 0.1 secs to compile + 0.1 secs to link + 0.1 secs in simulation End of Tool: VERILOG-XL 05.10.003-s Jan 19, 2008 18:01:41...
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This note was uploaded on 10/21/2009 for the course ECE 212 taught by Professor Rotenberg during the Spring '08 term at N.C. State.
- Spring '08