EE40_Fall08_Lecture35-41

EE40_Fall08_Lecture35-41 - EE40 Lecture 35-40 Connie...

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Slide 1 EE40 Fall 08 Connie Chang-Hasnain EE40 Lecture 35-40 Connie Chang-Hasnain Nov. 21, 24, 26, Dec. 1, 5, 8 Reading: Chap. 12 and Supplementary Notes Chap 4, 5 Slide 2 EE40 Fall 08 Connie Chang-Hasnain Chapter 12 MOSFET • OUTLINE – The MOSFET as a controlled resistor (Lec 35) – Pinch-off and current saturation (Lec 35) – MOSFET ID vs. VGS characteristic (Lec 35) – NMOS and PMOS I-V characteristics (Lec 35) – Load-line analysis; Q operating point; Bias circuits (Lec 36) – Small-signal equivalent circuits (Lec 37) – Common source amplifier (Lec 37, 38) – Source follower (Lec 38) – Common gate amplifier (Lec 39) – Gain (Lec 39) – Digital Gates (Lec 40-41)
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Slide 3 EE40 Fall 08 Connie Chang-Hasnain • The voltage applied to the GATE terminal determines whether – For an n-channel MOSFET, the SOURCE is biased at a lower potential (often 0 V) than the DRAIN (Electrons flow from SOURCE to DRAIN when V G > V T ) – For a p-channel MOSFET, the SOURCE is biased at a higher potential (often the supply voltage V DD ) than the DRAIN (Holes flow from SOURCE to DRAIN when V G < V T ) • The BODY terminal is usually connected to a fixed potential. – For an n-channel MOSFET, the BODY is connected to 0 V – For a p-channel MOSFET, the BODY is connected to V DD MOSFET Terminals Slide 4 EE40 Fall 08 Connie Chang-Hasnain MOSFET Structure DEVICE IN CROSS-SECTION “Metal” “Semiconductor” “Oxide” • In the absence of gate voltage, no current can flow between S and D. • Above a certain gate to source voltage V t (the “threshold”), electrons are induced at the surface beneath the oxide. (Think of it as a capacitor.) • These electrons can carry current between S and D if a voltage is applied. n P oxide insulator gate n “Metal” gate (Al or Si) D S G
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Slide 5 EE40 Fall 08 Connie Chang-Hasnain MOSFET • Symbol and subscript convention – Upper case for both (e.g. V D ) = DC signal (often as bias) – Lower case for both (e.g. v d ) = AC signal (often small signal) – Lower symbol and upper sub (e.g. v D ) = total signal = V D +v d • N MOS: Three regions of operation – V DS and V GS normally positive valus – V GS < V t :cut off mode, I DS =0 for any V DS – V GS > V t :transistor is turned on • V DS < V GS -V t : Triode Region • V DS > V GS -V t : Saturation Region • Boundary 2 2 2( ) 2( ) D GS t DS DS D GS t i K v V v v i K v V = - - = - GS t DS v V v - = 2 W KP K L = Slide 6 EE40 Fall 08 Connie Chang-Hasnain MOSFET • PMOS: Three regions of operation (interchange > and < from NMOS) – V DS and V GS Normally negative values – V GS > V t :cut off mode, I DS =0 for any V DS – V GS < V t :transistor is turned on • V DS > V GS -V t : Triode Region • V DS < V GS -V t : Saturation Region • Boundary 2 2 2( ) 2( ) D GS t DS DS D GS t i K v V v v i K v V = - - = - GS t DS v V v - = 2 W KP K L =
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This note was uploaded on 10/24/2009 for the course EE 40 taught by Professor Chang-hasnain during the Fall '07 term at University of California, Berkeley.

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EE40_Fall08_Lecture35-41 - EE40 Lecture 35-40 Connie...

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