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EE 40, FALL 2008
PROF. CHANGHASNAIN
HOMEWORK 9 SOLUTIONS
1. Hambley, P10.40
(a) The output is high if any input is high. This is because then one of the diodes
will be forward biased (ON) and pass the high input signal. If both inputs are
low, the output is low.
This is an OR gate.
(b) The output is high only if both inputs are high. This is because then both diodes
will be OFF. No current will ﬂow, causing a open at the output node, so there
will be no voltage drop across the resistor, making the output high.
This is an AND gate.
2. Hambley, P10.48
(a) Assume the diode is an open circuit, this gives us the following Voltage Divider
Equations:
v
1
= 4
*
200
200 + 200
= 2
V
,
v
2
= 4
*
100
300 + 100
= 1
V
Then the voltage cross the diode is
v
D
=
v
1

v
2
= 1 V. Since
v
D
is greater than
V
f
= 0
.
7
V
, the diode is not operating as an open circuit (it is forward biased)
(b) Assume the diode operates as a voltage source gives us:
KVL
v
1

v
2
= 0
.
7
KCL with supernode engulﬁng the diode:
v
1

4
200
+
v
1
200
+
v
2

4
300
+
v
2
100
= 0
Solving gives us:
v
1
= 1
.
829
V
,
v
2
= 1
.
129
V
. Applying KCL at node 1 gives us:
i
D
=
4

v
1
200

v
1
200
= 1
.
714
mA
, positive
Because the diode current is positive it is consistent with the model.
3. Hambley, P10.52
The dc output voltage is equal to the maximum amplitude of the ac source, which
is
v
L
= 20
√
2 = 28
.
28
V
. Assuming ripple is small we can assume that
v
L
is about
1
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EE 40, FALL 2008 PROF. CHANGHASNAIN HOMEWORK 9 SOLUTIONS
constant. This implies the peak inverse voltage to be double the value of
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 Fall '07
 ChangHasnain

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