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hw10sol

# hw10sol - ECE 3150 Homework 10 Solution Spring 2009...

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ECE 3150 Homework 10 Solution Spring 2009 Multiple Choice (3 pts each) For all multiple-choice problems below, we will use the CMOS parameters as k n = μ n C ox = 0.2mA/V 2 , k p = μ p C ox = 0.1mA/V 2 , and V thn =|V thp | = 0.7V. V DD = 5V and the Early effect is negligible. 1. For the CMOS inverter given below with (W/L) PMOS =2 and (W/L) NMOS =1, if v IN =0.7V, what is a good approximation of v OUT in the steady state? (a) 0.0V; (b) 0.7V; (c) 1.0V; (d) 2.5V; (e) 4.0V; (f) 4.3V ; (g) 5V. (g). For a matched inverter, NMOS has not really turned on, so v OUT at 5V. 2. Following Problem 1, if v IN =2.5V, what is a good approximation of v OUT in the steady state? (a) 0.0V; (b) 0.7V; (c) 1.0V; (d) 2.5V; (e) 4.0V; (f) 4.3V ; (g) 5V. (d). For the matched inverter, this is the switching threshold. 3. Following Problem 1, if v IN changes from 5V to 0V at t = 0, what is a good approximation for the time constant (minimal value) when v OUT 2245 5V? Assume that only the load capacitance C L needs to be considered. (a) 0.2ps; (b) 20ps; (c) 2ns; (d) 200ns; (e) 20 μ s; (f) 2ms; (g) 200ms. (c). We will estimate the saturation current of PMOS with a V OV =5V. I PMOSsat = 0.5 × 2 × 0.1mA/V 2 × 5 2 = 2.5mA. t switch = C × V DD /I PMOSsat = 1pF × 5/2.5mA = 2ns. 4. If now (W/L) PMOS =1 and (W/L) NMOS =2, if v IN =2.5V, what is a good approximation of v OUT in the steady state? (a) 0.0V; (b) 2.5V ; (c) 5.0V ; (d) cannot be determined. (a). Stronger NMOS with the switching threshold V M < 2.5V. Hence, v OUT should be closer to 0V. 5. For the pseudo-NMOS inverter given below with (W/L) PMOS = 2 and (W/L) NMOS = 1, now if v IN = 5.0V, what is a good approximation of v OUT in the steady state? (a) 0.0V; (b) 0.7V; (c) 1.0V; (d) 2.5V; (e) 4.0V; (f) 4.3V ; (g) 5V. (d). Now the PMOS and NMOS is matched again in strength. With v IN =5V, both PMOS and NMOS has V OV =5V, and therefore, it is a voltage divider at 2.5V. Notice now both PMOS and NMOS in the linear mode, but this will not change the answer. 1

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6. For the pass transistor logic below, what is the closest logical function implemented in Circuit A? (a) A(B+C) ; (b) A+BC ; (c) ABC ; (d) A+B+C ; (e) ) ( C B A + ; (f) BC A + ; (g) ABC . (c). V OUT is 1 only if A=B=C =1, unless it will be either in high-Z or 0. 7. For V DD =5V, V thn =1V and the signals ( A, B, C ) have strong “1” at full V DD values, what is the highest voltage V OUT can achieve in Circuit A in reasonable transit time? (a) 5.0V; (b) 4.5V; (c) 4.0V; (d) 3.5V; (e) 3.0V; (f) 2.5V; (g) 2.0V; (h) 1.5V. (c). Notice that if C has 5V, it will only enter subthreshold when the output of B reaches 4V. It is usually worse due to the existence of the body effect now that the source node is heavily reversed bias with respect to bulk. 8. For V DD =5V, V thn =1V and the signals ( A, B, C ) have strong “1” at full V DD values, what is the highest voltage V OUT can achieve in Circuit B in reasonable transit time? (a) 5.0V; (b) 4.5V; (c) 4.0V; (d) 3.5V; (e) 3.0V; (f) 2.5V; (g) 2.0V; (h) 1.5V. (e). Since the gate of the output transistor can only reach 4V, the output transistor will be in subthreshold when V OUT =3V. It is usually worse due to the existence of the body effect now that the source node is heavily reversed bias with respect to bulk.
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