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Unformatted text preview: Introduction to Microelectronics Chapter 5 S INGLE-S TAGE A MPLIFIERS WITH C URRENT M IRROR B IASING 5.1 Large-Signal Biasing with Resistive and Capacitive Elements We will first start the Chapter with resistor-transistor circuits, because the concept is a bit closer to what you have learned in the basic circuit course. Do remember that passive elements of resistors and inductors are very expensive in IC implementation in terms of the layout area, and their values are not very accurate. Therefore, our end goal is still to do the biasing and loads by transistors whenever possible. Conventionally this is called the active loads, in comparison with the passive loads if resistors are used. For many circuits, active loads are actually much better and more flexible than the resistive loads, as you will soon find out. For the resistor-transistor circuits in Fig. 1a (this circuit can serve as an amplifier or an inverter), we can find the circuit solution by: ( 29 ( 29 DD D D th GS n DS GS D V V RI V V k L W V V f L W I = +- = = 2 ' 2 ? , (5.1) where the ?= sign means that I D may be equal to the quadratic equation IF the saturation region condition of V DS > V Dsat = V OV can be satisfied. Because the equation in saturation (mostly depends on V GS and almost independent of V DS ) is much simpler than that in linear (depends almost equally on V GS and V DS ), the convenient way to solve this circuit is: 1. Assume NMOS in saturation. 2. Solve KVL ignoring the Early effect. Edwin C. Kan Page 5-1 10/25/2009 I D V DS Fixed V GS > V th R +- +- V DD V IN V OUT Fig. 5.1. (a) Resistive loads for transistor circuits; (b) Load-line solutions. Q 1 I D V Dsat =V GS V th V DS V DD-1/R large R small R r o (a) (b) 1 2 3 Introduction to Microelectronics 3. Check if V DS can make NMOS saturate by V DS > V Dsat = V OV . 4. If not, we will need to solve the V GS and V DS together in a coupled 2 2 matrix. We can also investigate the solution from the load line plot in Fig. 1b. We can see for a given V GS , different values of the load resistor can cause different behavior in the small-signal operations at the Q points 1, 2 and 3 as indicated. The small-signal model for the circuit is shown in Fig. 2. Fig. 5.2. The small signal model for the NMOS-resistor circuits. At the Q point 1 in Fig. 5.1, the transistor is in saturation, so r o is reasonably large, and there is a sufficient swing of V OUT where the transistor can remain in saturation and A v remains large. At the Q point 2 with a smaller load resistance, A v = g m (r o ||R) gets smaller due to R . At the operating point 3 with a larger load resistance, the transistor can be easily kicked out of saturation and enters into the linear region with very small r o . Again, A v will become small....
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