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Unformatted text preview: Introduction to Microelectronics Chapter 6 D IFF P AIR AND D IFFERENTIAL A MPLIFIER 6.1 The diff pair The diff pair is voted as the most popular analog circuits in ISSCC (International Solid- State Circuits Conference) 2002. The main purpose of the diff pair is to reflect the difference in its two inputs at its output, but insensitive to the average value of its two inputs. The difference of the two inputs is for the differential-mode operation which should have large gain, while the average of the two inputs is for the common-mode operation which should have a gain much smaller than 1. The ratio of the differential gain to the common-mode gain is named common- mode rejection ratio (CMRR) , which is one of the very important concepts in sampling a signal in a noisy environment. For example, if we are monitoring a pressure for structural integrity, it is difficult to know a priori what the absolute magnitude is. However, with a time delay circuit we can always compare the differential signal in time, which is much more immune to noise and drift. The operation of the diff pair, as shown in Fig. 6.1 for an NMOS implementation, is similar to a seesaw, although we can obtain a transconductance gain directly. where Q 1 and Q 2 are in the common-source implementation, with the large-signal voltage of the common node denoted as v S . Q 1 and Q 2 are driven by v G1 and v G2 , respectively, and we can always define the large-signal common-mode voltage v CM and the differential mode voltage v id as: Edwin C. Kan Page 6-1 10/25/2009 Fig. 6.1. The NMOS diff pair with resistive loads for simplicity. Q 1 Q 2 i D2 I- V SS v O2 R D R D i D1 v O1 +- v G2 v G1 +- v S Introduction to Microelectronics 2 1 2 1 2 G G id G G CM v v v v v v- = + = (6.1) 2 2 2 1 id CM G id CM G v v v v v v- = + = (6.2) Notice that we have denoted the differential-mode voltage v id as in the small-signal form. Strictly speaking, it should be a large-signal term, but since it is most often used in small-signal AC analysis, we will use v id here. We will first investigate the large-signal common-mode operation for the diff pair in Fig. 6.1. For clarity, the current components are redrawn in Fig. 6.2. We will first ignore the Early effect and the body effect. From the circuit, we know that once the biasing current I is set in the common mode , V OVcm , V GS1 , V GS2 , v O1 , and v O2 are known, only v S will be determined by v CM, . V OVcm is the common-mode gate overdrive that gives I/2 current in each branch. We can write down the relation as: v S + V GS1 = v CM ; v S = V CS V SS (6.3) where V CS is the voltage drop across the biasing current source (or if by active-load current Edwin C. Kan Page 6-2 10/25/2009 Fig. 6.2. Analysis of the NMOS diff pair in the common mode....
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