Midterm Wi05

Midterm Wi05 - EOE-700 Digital Signal Processing Winter...

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Unformatted text preview: EOE-700 Digital Signal Processing Winter 2005 Midterm Exam Feb. 16, 2005 MIDTERM EXAMINATION Name: Instructions: 0 Do not turn over this cover page until instructed to do so. 0 You will have 120 minutes to complete this exam. 0 You are allowed to consult the letter—sized piece of paper which you have prepared beforehand. You are not allowed to consult any other books, notes, people, elves, escorts, or exemplars. 0 Please write clearly and include sufficient explanation with all of your answers. 0 If you write on the backs of the pages, indicate this so the grader does not miss your work. o Do not unstaple the test pages. P. Schniter, 2005 1 W‘mjm'l @ “bi-ab ohakvaia,:7 @) vealed»? 3- («CHIS Lax/Ta c) (9M ' 1. We are interested in decimating a real-valued input by factor 12 using the three-stage structure .1 below. We want to prevent aliasing in the output spectrum up to bandwidth we radians. Assume that the input is “fullband,” i.e., has uniform spectral density. xlnl How) i2 Hie) 12 mm] Specify the passband and stopband edges of H0(z), H1(z), and H2(z) which leave the widest possible transition band(s) to ensure the aliasing behavior described above. Summarize your answers in the table below. It is sufficient to specify the positive edge frequencies. (Hint: Consider the design of each stage separately.) 2. Say that we are interested in decimation by factor D 2 2K , where K is a positive integer, using the simple “boxcar” master filter H z = .D:1 24. 1—0 (a) For general D, draw a block diagram for the standard single—stage polyphase decimation structure. Be sure to incorporate the particular structure of the polyphase filters for this problem. (b) For the system in (a), how many multiplicatio are required per output point? How many additions? How many signal values need to be tored at any given time? (c) Notice that H(z) : (1 + z‘l)(1 + 2’2)(1 + z‘ + 2—21“1 an efficient 4-stage decimation structure for D 16 and draw its block diagram. If possible, ). Using this fact, construct implement each stage using polyphase techniq es. (Hint: The new structure is a cascade of simple, identical stages.) (d) For the system in (c), how many multiplicatiots are required per output point? How many additions? How many signal values need to be tored at any given time? (e) What advantages, if any, does the multistage decimator in (c) have over the traditional polyphase decimator in (a)? (Hint: Use your ailswers from parts (b) and 3. Consider the 3-branch filterbank illustrated below. v (a) To ensure aliasing cancellation, what conditio must the filters {Hk(z)}%=0 and {Gk(z)}i=0 satisfy? (b) To ensure delay-E perfect reconstruction, wh conditions must the filters {Hk(z)}i=0 and {019(2) i=0 satisfy? P. Schniter, 2005 2 mm m z -, | ‘ Hum h a“ Maturity: my.” I r A ,l .i J 4 ,H 4 up w HMMHH-Wm rill!) iHIIitiii-vt' ‘ r-l I ,n w u w um l-H'hll J r I ( c) m, ., “mew EOE-700 Digital Signal Processing Winter 2005 Midterm Examination Feb. 19, 2005 MIDTERM SOLUTIONS 1. The design of each filter is based on the desired-signal—bandwidth at the input to that stage and the decimation factor of that stage. Recall that the desired-signal—bandwidth in Y(ej“’) is we radians, and that the total decimation factor is 2 X 2 x 3 = 12. Without loss of generality, we consider only positive frequencies below. nip] $2qu $[nl H00?) 12 111(2) 1 2 H2(Z) l 3 vim] The signal will be decimated by 12 to generate the output Hence, the desired—signal— bandwidth of X (63“) is T—z‘l, and the passband edge of H0(z) should be Since the first stage decimates by 2, we can choose the transition band to extend symmetrically around 12! in order to prevent aliasing into the desired-signal region. Hence, the stopband edge should start at 71' ~ (See figure below, which is unfortunately not drawn to scale!). IX (ej“)| The signal {201 will be decimated by 6 to generate the output Hence, the desired-signal- bandwidth of X1(ej“’) is £69, and the passband edge of H1(z) should be 36%. Since the second stage decimates by 2, we can choose the transition band to extend symmetrically around % in order to prevent aliasing into the desired—signal region. Hence, the stopband edge should start at 1r — $61. (See figure below, which is unfortunately not drawn to scale!). P. Schniter, 2005 1 The signal {x2 will be decimated by 3 to generate the output Hence, the desired-signal- bandwidth of X2 (81“) is 332, and the passband edge of H2 (2) should be Since the last stage decimates by 3, we can choose the first transition band to extendtsymmetrically around g in order to prevent aliasing into the desired-signal region. Hence, the firbt stopband edge should start at 2?" ‘ 9’62. But, after decimation, the region [ — gi, 7r) will also avoid the desired-signal region, and so we can apply a stopband edge at 1r — (See figure below.). |X2(e’“)| unddsi red To summarize: — stopband edges) w e <2) P. Schniter, 2005 g 1 ~ 2. (a) Since the master filter has exactly D coefficients equal to one, the polyphase filter have length one and coefficient value equal to one. I.e., Hk(z) = 1 Vk. Thus, the D-branch polyphase structure reduces to the structure below. (b) As seen from the preceding block diagram, there are zero multiplications and D — 1 additions. The structure stores D values. (0) For the D = 16 case, we have the expansion H(z) = (1 + z“l)(1 + 2—2)(1 + 2—4)(l + Z“). Thus H (2) can be implemented by cascading four filters, each with two non—zero coefficients. Breaking the 16-downsampler into a cascade of an 8—downsamp1er and a 2-downsampler, we can use the Noble identity to reverse the order of the (1+z_8) filter and the 8—downsampler. In doing so, the Noble identity specifies that (1 + 243) becomes (1 + 2— 1). The 8—downsampler can be broken up, and the process repeated, until we have four identical stages, each decimating by factor 2. Each stage can be implemented using two polyphase branches. See below. —’1+z‘_J—‘ll+z‘2Hvl+z_—Hi+:H‘18‘lei—‘ {1+2‘Tl—‘li+z_2 1+2‘4}—-E8j—-L1+2‘1J—‘L12J—~ ~1+2-1 1+z‘2 1+z—4 ifl—fl2~(1+z—j—l12} *"F1+z‘1 1+z‘2 12 12 1+2‘ 12 P. Schniter, 2005 3 (d) The preceding block diagram shows zero multiplications. The fourth stage requires 1 addi— tion per system output point; the third stage generates 2 outputs per system output, thus requiring 2 additions; the second stage generates 4 outputs per system output, thus requiring 4 additions; and the first stage generates 8 outputs per system output, thus requiring 8 ad— ditions. In total, we need 8 + 4 + 2 + 1 = 15 additions. The block diagram stores two values per stage, for a total of 8 values. (e) Extrapolating the results of (d) to general D, we find that both structures require the same number of multiplications and additions per output point. But the multi-stage structure requires 2K storage elements rather that 2K, which is advantageous for large K. 3. (a) The system output can be written This follows from the fact that downsampler output on the kth branch equals 2 1 l - 1r 1 . .n 3 E X(25e523‘p)Hk(2561271’). :0 The system output can be written in vector / matrix form: it Hot?) H19; H29) 00(2) [X(z) x1261?) X(ze2'%)] Hamil?) Hfize’T") medial) ale) H0(zej4Tfl) HfizefTfl) H2(zej3§r‘) 02V) ya) = % For aliasing cancellation, the terms X (zej 2531) and X (zej 93—") must not contribute to Y(z). This is satisfied when (b) For perfect reconstruction with delay K E Z, we need that Y(z) = z“X This requires that 1 2 H _ 3 Z Hk(z)Gk(z) 16:0 in addition to aliasing cancellation. a 1% P. Schniter, 2005 4 4|; , w | mm H lmww.’ |t Ni ii 1 i l i 1 ll ‘ H l uuu- i MW“ in rt: .1 t, l i I l i l u w - : l; , Jam“ ...
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Midterm Wi05 - EOE-700 Digital Signal Processing Winter...

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