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CPU12RG - Freescale Semiconductor Inc Reference Guide...

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© Motorola, Inc., 2001 CPU12RG/D Rev. 2, 11/2001 CPU12 Reference Guide (for HCS12 and original M68HC12) Reference Guide Figure 1. Programming Model 7 15 15 15 15 15 D X Y SP PC A B N S X H I Z V C 0 0 0 0 0 0 7 0 CONDITION CODE REGISTER 8-BIT ACCUMULATORS A AND B 16-BIT DOUBLE ACCUMULATOR D INDEX REGISTER X INDEX REGISTER Y STACK POINTER PROGRAM COUNTER OR STOP DISABLE (IGNORE STOP OPCODES) RESET DEFAULT IS 1 CARRY OVERFLOW ZERO NEGATIVE MASK (DISABLE) IRQ INTERRUPTS HALF-CARRY (USED IN BCD ARITHMETIC) MASK (DISABLE) XIRQ INTERRUPTS RESET OR XIRQ SET X, INSTRUCTIONS MAY CLEAR X BUT CANNOT SET X Freescale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..
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CPU12RG/D 2 CPU12 Reference Guide (for HCS12 and original M68HC12) MOTOROLA Stack and Memory Layout Interrupt Vector Locations Notation Used in Instruction Set Summary SP BEFORE INTERRUPT SP AFTER INTERRUPT HIGHER ADDRESSES LOWER ADDRESSES RTN LO RTN HI Y LO Y HI X LO X HI A B CCR STACK UPON ENTRY TO SERVICE ROUTINE IF SP WAS ODD BEFORE INTERRUPT STACK UPON ENTRY TO SERVICE ROUTINE IF SP WAS EVEN BEFORE INTERRUPT SP +8 RTN LO SP +9 SP +9 SP +10 SP +6 Y LO RTN HI SP +7 SP +7 RTN HI RTN LO SP +8 SP +4 X LO Y HI SP +5 SP +5 Y HI Y LO SP +6 SP +2 A X HI SP +3 SP +4 X HI X LO SP +4 SP CCR B SP +1 SP +1 B A SP +2 SP –2 SP –1 SP –1 CCR SP $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB $FFF8, $FFF9 $FFF6, $FFF7 $FFF4, $FFF5 $FFF2, $FFF3 $FFC0–$FFF1 Power-On (POR) or External Reset Clock Monitor Reset Computer Operating Properly (COP Watchdog Reset Unimplemented Opcode Trap Software Interrupt Instruction (SWI) XIRQ IRQ Device-Specific Interrupt Sources CPU Register Notation Accumulator A — A or a Index Register Y — Y or y Accumulator B — B or b Stack Pointer — SP, sp, or s Accumulator D — D or d Program Counter — PC, pc, or p Index Register X — X or x Condition Code Register — CCR or c Freescale Semiconductor, I Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com nc. ..
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CPU12RG/D MOTOROLA CPU12 Reference Guide (for HCS12 and original M68HC12) 3 Explanation of Italic Expressions in Source Form Column abc A or B or CCR abcdxys A or B or CCR or D or X or Y or SP. Some assemblers also allow T2 or T3. abd A or B or D abdxys A or B or D or X or Y or SP dxys D or X or Y or SP msk8 8-bit mask, some assemblers require # symbol before value opr8i 8-bit immediate value opr16i 16-bit immediate value opr8a 8-bit address used with direct address mode opr16a 16-bit address value oprx0_xysp Indexed addressing postbyte code: oprx3 ,– xys Predecrement X or Y or SP by 1 . . . 8 oprx3 , + xys Preincrement X or Y or SP by 1 . . . 8 oprx3 , xys Postdecrement X or Y or SP by 1 . . . 8 oprx3 , xys + Postincrement X or Y or SP by 1 . . . 8 oprx5,xysp 5-bit constant offset from X or Y or SP or PC abd , xysp Accumulator A or B or D offset from X or Y or SP or PC oprx3 Any positive integer 1 . . . 8 for pre/post increment/decrement oprx5 Any integer in the range –16 . . . +15 oprx9 Any integer in the range –256 . . . +255 oprx16 Any integer in the range –32,768 . . . 65,535
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  • Spring '09
  • chavez
  • Trigraph, Broadway – Lafayette Street, Forest Hills – 71st Avenue, Freescale Semiconductor, Freescale Semiconductor, Inc

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