This preview shows pages 1–3. Sign up to view the full content.
This preview has intentionally blurred sections. Sign up to view the full version.View Full Document
Unformatted text preview: Figure 4 shows one of many transformations of the circuit diagram in Figure 2 into the format shown in Figure 3. There are several different organizations of the order of the transistors for the A, B, C, D, and E inputs, different organizations requiring differing numbers of wires in the intra-cell wiring channel. I have labeled source and drain sides of the transistors in Figure 4 to correspond to their labeling in Figure 2. Vcc Ground Ground Intra-Cell Wiring Channel Inter-Cell Wiring Channel Cell I/O N-Type Well Figure 3: Illustration of general topology for layout of PMOS and of NMOS transistors in rows. Vcc Ground Ground A B C D E s s s s s d d d d d d output s s s s s d d d d Note: You can not connect polysilicon to a diffusion (theres always a thin, gate oxide separating them, by construction. Figure 4: Example of row-based layout for circuit in Figure 2. In Figure 4, not that the drain connection from the PMOS transistor extends to a metal line using the diffusion layer in order to run under the...
View Full Document
- Spring '09