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lecture_note10 - CpE 390: Microprocessor Systems Lecture 10...

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Stevens Institute of Technology 1 CpE 390: Microprocessor Systems Lecture 10 68HC12 Serial Interface – SPI
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Stevens Institute of Technology 2 The SPI Function - A serial synchronous communication protocol (while SCI is a serial asynchronous communication protocol) - Mainly used in interfacing with peripherals such as shift registers, LED/LCD display drivers, memory components with serial interface, or A/D and D/A converters that does not need high speed. - There are two types of device in a network that uses SPI protocol: a master and one or multiple slaves. - Data transfer in SPI protocol can only be initiated by a master device. - A microcontroller can be a master or slave device. When configured as a slave device, a microcontroller would respond to the transfer request only when its slave select (SS) input is asserted.
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Stevens Institute of Technology 3 Figure 9.8 Multiple serial interface (SCIs and SPI) block diagram SCI0 RxD0 RxD1 TxD0 TxD1 SCI1 MISO/SISO MOSI/MOMI SCK CS/SS DDRS/IOCTLR PORT S I/O DRIVERS SPI PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 68HC12 Note. B family members (912B32, 912BC32, and 912BE32) do not have SCI1 4 PORTS pins required for SPI: SDI/MISO: master-in-slave-out (serial data input) – msb sent first SDO/MOSI: master-out-slave-in (serial data output) – msb sent first SCK: serial clock: synchronize data movement ~CS/~SS: chip select (or slave select)
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Stevens Institute of Technology 4 SPI Operation - The 8-bit data register in the master and the 8-bit data register in the slave are linked together to form a distributed 16-bit shift register. - When a data transfer operation is performed, this 16-bit register is serially shifted eight bit positions by the SCK clock from the master so the data is effectively exchanged between the master and the slave. - Related Registers - Two control registers: SP0CR1 & SP0CR2 . - Baud rate register SP0BR . -Statusregister( SP0SR ) - Data written into the SP0DR register of the master becomes the output data for the slave. - Data read from the SP0DR register of the master after a transfer operation is the input data to the slave.
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Stevens Institute of Technology 5 76543210 value after reset 00000100 MSTR CPOL CPHA SSOE SPIE SPE SWOM LSBF Figure 9.20 SPI control register 1 (SP0CR1) SPIE: SPI interrupt enable bit 0 = SPI interrupts are inhibited 1 = SPI interrupt is requested every time the SPIF or MODF status flag is set. SPE: SPI system enable bit 0 = SPI hardware is initialized but is in the disabled state 1 = SPI enabled and pins PS4-PS7 are dedicated to SPI function SWOM: Port S wired-OR mode bit Controls only pins PS4-PS7. 0 = PS4-PS7 output buffers operate normally 1 = PS4-PS7 output buffers behave as open-drain outputs MSTR: SPI master/slave mode select bit 0 = slave mode 1 = master mode CPOL and CPHA: SPI clock polarity, clock phase bits Functions are shown in Figure 9.18a and 9.18b SSOE: slave select output enable bit The SS output feature is enabled only in master mode by asserting the SSOE and DDRS7.
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This note was uploaded on 10/27/2009 for the course ECE 5 taught by Professor Chavez during the Spring '09 term at Stevens.

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lecture_note10 - CpE 390: Microprocessor Systems Lecture 10...

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