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lecture_note12 - CpE 390: Microprocessor Systems Lecture 12...

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Stevens Institute of Technology 1 CpE 390: Microprocessor Systems Lecture 12 68HC12 Analog to Digital Converter (2)
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Stevens Institute of Technology 2 Example 10.5 Write a subroutine to initialize the ATD0 module of the 912DG128 with the following parameters: - Nonscan mode - Select channels 0 to 7 - Enable fast flag clear feature - Stop ATD in wait mode - Disable interrupt - Finish current conversion then freeze when BDM becomes active - Select 10-bit operation and set sample time to 4 ATD clock periods - Set prescale factor to 4 for 8 MHz E clock Solution: Settings of ATD control registers as follows: ATD0CTL2 - Enable ATD (set bit 7 to 1) - Select fast flag clear all (set bit 6 to 1) - Stop ATD when in wait mode (set bit 5 to 1) - Disable ATD interrupt (set bit 1 to 0) - Clear all other bits - Write the value $E0 into this register ADPU AFFC AWAI 00 0 ASCIE ASCIF 1 1 1 0 0
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Stevens Institute of Technology 3 ATD0CTL3 - Complete the current instruction when the BDM becomes active - Write the value $02 into this register ATD0CTL4 - Select 10-bit operation (set bit 7 to 1) - Set sample time to 4 ATD clock periods (set bits 6. .5 to 01) - Set prescale factor to 4 to select 2 MHz as the ATD clock source frequency. - Write the value $A1 into this register. ATD0CTL5 - Set conversion sequence length to 8 (set bit 6 to 1) - Select nonscan mode (set bit 5 to 0) - Select multiple channel mode (set bit 4 to 1) - Select channels 7 to 0 (set bits 3. .0 to 0000) - Write the value $50 to this control register 0 0 0 00 0 FRZ1 FRZ0 1 0 S10BM SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 1 0 1 0 1 0 0 0 0 S8CM SCAN MULT CD CC CB CA 1 0 0 0 1 0 0
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Stevens Institute of Technology 4 S8CM Channel Signal Result in ADRx if MULT = 1 CD CC CB CA 0 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Reserved VRH VRL (V RH + V RL )/2 Test/reserved ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 Notes: Shaded bits are “don’t care” if the MULT bit = 1 and the entire block of four or eight channels makes up a conversion sequence. When MULT bit = 0, all four bits (CD, CC, CB, CA) must be specified and a conversion sequence consists of four or eight consecutive conversions of the single specified channel.
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Stevens Institute of Technology 5 Example 10.6 Write a program to perform A/D conversion on the analog signal connected to the AN7 pin. Collect 20 A/D conversion results and store them at memory location starting from $800. Use the same configuration as in Example 10.4. Solution: - Write to the ATDCTL5 register five times and collect four samples each time. - Wait until the SCF flag of the ATDSTAT register is set to 1 and then collect the samples. #include "d:\miniide\hc12.inc" org $1000 ldx #$800 ; use index register X as a pointer to the buffer jsr ATD_init ; initialize the ATD converter ldy #5 loop5 movb #$07,ATDCTL5 ; start an A/D conversion sequence brclr ATDSTAT0,$80,* movw ADR0H,2,x+ ; collect and save the conversion result (left- justified) movw ADR1H,2,x+ ; post-increment the pointer by 2 movw ADR2H,2,x+ ; movw ADR3H,2,x+ ; dbne y,loop5 swi end
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Stevens Institute of Technology 6 From example 10.4.
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This note was uploaded on 10/27/2009 for the course ECE 5 taught by Professor Chavez during the Spring '09 term at Stevens.

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lecture_note12 - CpE 390: Microprocessor Systems Lecture 12...

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