W09 314 HW10 all - EECS 314 Winter 2009 Homework set 10 Students name Discussion section(Last First write legibly use ink(use ink Instructor is not

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EECS 314 Winter 2009 Homework set 10 Student’s name ___________________________ Discussion section # _______ (Last, First, write legibly, use ink) (use ink) Instructor is not responsible for grading and entering scores for HW papers lacking clear information in the required fields above © 2009 Alexander Ganago Page 1 of 2 Problem 1 Combinations of Logic Gates (60 points) Consider the combination of NAND gates shown here: Prove that it acts as the OR gate, that is other words, it performs the same logic operation on any combination of the two inputs A and B as the gate OR does. Use the truth table of OR, reproduced here for your convenience; fill in the blank table (on the left), and compare it with the given table for OR. If the two truth tables are identical, the logic operations are identical. Show your work below and/or on additional pages. Continuedon the next page.
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EECS 314 Winter 2009 Homework set 10 Student’s name ___________________________ Discussion section # _______ (Last, First, write legibly, use ink) (use ink) Instructor is not responsible for grading and entering scores for HW papers lacking clear information in the required fields above © 2009 Alexander Ganago Page 2 of 2 Problem 1, continued Repeat for the NOR operation. Show your work below and/or on additional pages. This diagram shows a combination of NAND and NOR gates, which acts as a logic gate. Determine its type. A. AND B. OR C. NAND D. NOR E. None of the above. Show your work on additional pages.
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EECS 314 Winter 2009 Homework set 10 Student’s name ___________________________ Discussion section # _______ (Last, First, write legibly, use ink) (use ink) Instructor is not responsible for grading and entering scores for HW papers lacking clear information in the required fields above © 2009 Alexander Ganago Page 1 of 2 Problem 2 Digital Circuits with Memory: Set-Reset The Big Picture The circuit shown on this diagram is called SR flip-flop, where SR stands for Set-Reset. On the left, it is shown as a pair of NOR gates; on the right, the same circuit is shown as a functional block. The two outputs are logic complements of each other: if Q equals “1” then Q _ equals “0” and vice versa . The inputs R and S are not allowed to equal “1” at the same time; if both inputs equal “0” then the output Q is kept in its previous state indefinitely (while the power is applied to the circuit), which makes it a simple memory cell. One of the practical applications of this circuit is to avoid the effect of so-called switch bounce. The “pull-down” resistors ensure LOW voltage at the inputs when the switch is open. When the switch is flipped from A to B, the input voltage V A definitely goes to LOW but the switch may bounce and temporarily disconnect input B from the source as shown for the intervals of time labeled 2 and 4 on the sketch below. Similarly, when the switch is flipped from B to A,
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This note was uploaded on 10/28/2009 for the course EECS 314 taught by Professor Ganago during the Winter '07 term at University of Michigan.

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W09 314 HW10 all - EECS 314 Winter 2009 Homework set 10 Students name Discussion section(Last First write legibly use ink(use ink Instructor is not

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