W09 314 HW10 solution

W09 314 HW10 solution - EECS 314 Winter 2009 Homework set...

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EECS 314 Winter 2009 Homework set 10 Student’s name ___________________________ Discussion section # _______ (Last, First, write legibly, use ink) (use ink) Instructor is not responsible for grading and entering scores for HW papers lacking clear information in the required fields above Problem 1 solution Lets first write the truth tables for the AND, OR, NAND, and NOR logic gates. AND: Input 1 Input 2 Output 0 1 0 1 1 1 0 0 0 1 0 0 OR: Input 1 Input 2 Output 0 1 1 1 1 1 0 0 0 1 0 1 NAND: Input 1 Input 2 Output 0 1 1 1 1 0 0 0 1 1 0 1 NOR: Input 1 Input 2 Output 0 1 0 1 1 0 0 0 1 1 0 0 Part 1: Let us call the output of the NAND gate with A as the input A’ and call the output of the NAND gate with B as the input B’. Then A’ and B’ are the inputs to the NAND gate with output C.
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A B A’ B’ C 0 0 1 1 0 1 0 0 1 1 0 1 1 0 1 1 1 0 0 1 Based on this truth table we can conclude that the combination of NAND gates does act as an OR gate. Part 2: Again let us call the output of the NAND gate with A as the input A’ and call the output of the NAND gate with B as the input B’. Then A’ and B’ are the inputs to the NAND gate with output C’. C’ is a double input to the NAND gate with output C. We’ll break C’ into two inputs C’1 and C’2 for convenience. A B A’ B’ C’1 C’2 C 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 Based on this truth table we can conclude that the combination of NAND gates does act as an NOR gate. Part 3: Now let us call the output of the NOR gate with A as the input A’ and call the output of the NAND gate with B as the input B’. Then A’ and B’ are the inputs to the NAND gate with output C’. C’ is a double input to the NAND gate with output C. We’ll break C’ into two inputs C’1 and C’2 for convenience. A B A’ B’ C’1 C’2 C 0 0 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 Based on this truth table we can conclude that the combination of NAND gates acts as an NOR gate.
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EECS 314 Winter 2009 Homework set 10 Student’s name Discussion section # (Last, First, write legibly, use ink) (use ink) Instructor is not responsible for grading and entering scores for HW papers lacking clear information in the required fields above Problem 2 The Assignment R S Comment Q 0 1 Q fd1 7 1CS V’L(’te of Q 1 0 /s aI vc(u 0+ 0 0 Assume that initially Q 0 0 0 1 0 Assume that initially Q 1 —---— —— —-—-—— I - - --r-rn - —— IL - i___ - - Time © 2009 Alexander Ganago Page 2 of 2 , -‘ Part 1 (15 points) Determine the truth table for the SR flip-flop. Remember that inputs R and S are not allowedto equal “1” at the same time. Fill in the table: Show your work on a separate page. Part 2 (25 points) For this circuit, sketch the output waveforms Q and Q on the timing diagram below. Carefully explain what happens during the time \/ intervals 1,2, 8, and 9.
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This note was uploaded on 10/28/2009 for the course EECS 314 taught by Professor Ganago during the Winter '07 term at University of Michigan.

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W09 314 HW10 solution - EECS 314 Winter 2009 Homework set...

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