Lecture 25

Lecture 25 - EEE 352: Lecture 25 * Complementary MOS...

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EEE 352: Lecture 25 Portion of Pentium chip. * Complementary MOS Inverters * Dynamic Random Access Memory * Static Memory * Growth of the VLSI Density * Moore’s Law * Scaling the MOSFET
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n-Channel Inverter V DS t 0 V DS t 0 V DS N When INPUT goes HIGH The OUTPUT goes LOW A HIGH input voltage turns the transistor ON, which decreases its resistance to a value much less than the RESISTOR, pulling the output voltage to GROUND level.
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p-Channel Inverter V DS t 0 V DS t 0 V DS P When INPUT goes LOW The OUTPUT goes HIGH A LOW input voltage turns the transistor ON, which decreases its resistance to a value much less than the RESISTOR, pulling the output voltage to V DS level.
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The Complementary MOS Inverter The RESISTORS dissipate too much power. We eliminate them by combining the two circuits into one as a PUSH-PULL. V DS P + V DS N = V DS P N
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The Complementary MOS Inverter V DS P N t 0 V DS t 0 V DS When INPUT goes LOW, The OUTPUT goes HIGH When INPUT goes HIGH, The OUTPUT goes LOW A LOW input voltage turns the p -device ON, pulling the output voltage to V DS level. A HIGH input voltage turns the n -device ON, pulling the output to GROUND level. The OFF transistor dissipates little power, so the CMOS circuit dissipates almost ZERO power in the standby state—dissipation only occurs during the SWITCH process when both transistors are ON.
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The Complementary MOS Inverter INTEL: S. Tyagi et al., IEDM 2000
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p-well pseudo n-well P+ P+ Field oxide N+ N+ Field oxide Field oxide n-type substrate Poly-silicon (or silicide) gates and interconnect lines. Oxides
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This note was uploaded on 10/28/2009 for the course EEE 352 taught by Professor Ferry during the Fall '08 term at ASU.

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Lecture 25 - EEE 352: Lecture 25 * Complementary MOS...

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