Lecture 37

Horizontalwiresdonotcompete wellwithfinfets

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Unformatted text preview: ic
to
these
wires
 as
we
do
to
the
FINFETs —we
must
have
more
 ac?ve
device
area
than
 the
Si
real
estate
we
 u?lize.
 First
we
have
to
fit
the
wires
onto
the
surface:
 tG
 tox
 wire
 wire
 Si
substrate
 d
 width
 W
 pitch
 But
we
cannot
waste
surface
area:
 Hence
 If
we
use
a
high‐K
dielectric
so
that
tox
~
2
nm
and
a
gate
metaliza?on
of
tG
~
 3
nm,
then
 Thus,
the
minimum
wire
diameter
is
about
5
...
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This note was uploaded on 10/28/2009 for the course EEE 352 taught by Professor Ferry during the Fall '08 term at ASU.

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