Lecture 37 - EEE352Lecture37 Nanowires...

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EEE 352—Lecture 37 Nanowires Semiconduc8ng nanowires * Etched wires * Grown wires * Useful things
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This device makes good sense when as it gives more effec8ve device width. The Intel tri‐gate transistor builds on the idea of nanowires, in that the device is an accumula8on of nanowires. L sp
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How does real estate cost impact device design? In a FINFET, in order to create more device area per unit area of Si, we need to have Si substrate Fin Fin W pitch d width h height Novel devices can only succeed if they give more ac?ve area per unit area of Si.
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What is the impact of this on e.g. Nanowires? Si substrate W pitch d width wire wire thickness of metal gate t G thickness of oxide t ox We have to apply the same logic to these wires as we do to the FINFETs —we must have more ac?ve device area than the Si real estate we u?lize.
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First we have to fit the wires onto the surface: Si substrate W pitch d width wire wire t G t ox But we cannot waste surface area:
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Hence If we use a high‐K dielectric so that t ox ~ 2 nm and a gate metaliza?on of t
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